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authorHans Verkuil <hverkuil-cisco@xs4all.nl>2021-05-31 15:31:11 +0200
committerHans Verkuil <hverkuil-cisco@xs4all.nl>2021-05-31 15:43:26 +0200
commiteb7831ef61e22dc5be20f9da50e804917aa54f8f (patch)
tree1134ecefe1523752572109865dacece9ec10723f /calc-gtf-cvt.cpp
parenteaee00f196ec4081b2a2dfcde71f46b9097e9bf5 (diff)
edid-decode: add DisplayID 2.0 E8 Type X support
Implement the changes for Type X defined in the DisplayID 2.0 E8 errata document. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'calc-gtf-cvt.cpp')
-rw-r--r--calc-gtf-cvt.cpp18
1 files changed, 13 insertions, 5 deletions
diff --git a/calc-gtf-cvt.cpp b/calc-gtf-cvt.cpp
index bc32ea0..36f89f2 100644
--- a/calc-gtf-cvt.cpp
+++ b/calc-gtf-cvt.cpp
@@ -128,7 +128,8 @@ void edid_state::edid_gtf_mode(unsigned refresh, struct timings &t)
// If rb == RB_CVT_V3, then alt means that rb_h_blank is 160 instead of 80.
timings edid_state::calc_cvt_mode(unsigned h_pixels, unsigned v_lines,
double ip_freq_rqd, unsigned rb, bool int_rqd,
- bool margins_rqd, bool alt, unsigned rb_h_blank)
+ bool margins_rqd, bool alt, unsigned rb_h_blank,
+ double add_vert_time)
{
timings t = {};
@@ -149,6 +150,7 @@ timings edid_state::calc_cvt_mode(unsigned h_pixels, unsigned v_lines,
double h_blank = (rb == RB_CVT_V1 || (rb == RB_CVT_V3 && alt)) ? 160 : 80;
double rb_v_fporch = rb == RB_CVT_V1 ? 3 : 1;
double refresh_multiplier = (rb == RB_CVT_V2 && alt) ? 1000.0 / 1001.0 : 1;
+ double rb_min_vblank = CVT_RB_MIN_VBLANK;
double h_sync = 32;
double v_sync;
@@ -156,6 +158,11 @@ timings edid_state::calc_cvt_mode(unsigned h_pixels, unsigned v_lines,
double v_blank;
double v_sync_bp;
+ if (rb == RB_CVT_V3 && add_vert_time) {
+ if (add_vert_time + rb_min_vblank <= 1000000.0 / ip_freq_rqd / 4.0)
+ rb_min_vblank += add_vert_time;
+ }
+
if (rb == RB_CVT_V3 && rb_h_blank) {
h_blank = rb_h_blank & ~7;
if (h_blank < 80)
@@ -198,9 +205,9 @@ timings edid_state::calc_cvt_mode(unsigned h_pixels, unsigned v_lines,
h_sync = floor(total_pixels * 0.08 / CELL_GRAN) * CELL_GRAN;
pixel_freq = floor((total_pixels / h_period_est) / clock_step) * clock_step;
} else {
- double h_period_est = ((1000000.0 / v_field_rate_rqd) - CVT_RB_MIN_VBLANK) /
+ double h_period_est = ((1000000.0 / v_field_rate_rqd) - rb_min_vblank) /
(v_lines_rnd + vert_margin * 2);
- double vbi_lines = floor(CVT_RB_MIN_VBLANK / h_period_est) + 1;
+ double vbi_lines = floor(rb_min_vblank / h_period_est) + 1;
double rb_min_vbi = rb_v_fporch + v_sync + CVT_MIN_V_BPORCH;
v_blank = vbi_lines < rb_min_vbi ? rb_min_vbi : vbi_lines;
double total_v_lines = v_blank + v_lines_rnd + vert_margin * 2 + interlace;
@@ -237,13 +244,14 @@ timings edid_state::calc_cvt_mode(unsigned h_pixels, unsigned v_lines,
return t;
}
-void edid_state::edid_cvt_mode(unsigned refresh, struct timings &t)
+void edid_state::edid_cvt_mode(unsigned refresh, struct timings &t, unsigned rb_h_blank,
+ double add_vert_time)
{
unsigned hratio = t.hratio;
unsigned vratio = t.vratio;
t = calc_cvt_mode(t.hact, t.vact, refresh, t.rb & ~RB_ALT, t.interlaced,
- false, t.rb & RB_ALT);
+ false, t.rb & RB_ALT, rb_h_blank, add_vert_time);
t.hratio = hratio;
t.vratio = vratio;
}

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