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authorArnd Bergmann <arnd@arndb.de>2015-10-23 22:04:49 +0200
committerArnd Bergmann <arnd@arndb.de>2015-10-23 22:04:49 +0200
commita3de778b1faecdb4a8709d96ac0ab3a61b40e898 (patch)
treebc132491ddbbda9ce54f10dcb36ca95de849c040
parent7007c60c28b2f1572b488513d94472046a79fa20 (diff)
parent848dd6a87a10bd24b5a4c8b84eaba3cdd0ec7a19 (diff)
Merge tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt
Merge "STi DT changes for v4.4, round 2" from Maxime Coquelin: - Use STiH418's A9 PLL - Add Ethernet support to STiH407 family * tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti: ARM: STi: DT: Add support for stih418 A9 pll ARM: dts: Enable Ethernet on STi's B2199 board ARM: dts: Enable Ethernet on STi's B2120 boards ARM: dts: Add Ethernet node to STiH407 family ARM: dts: Fix RGMII pinctrl timings
-rw-r--r--arch/arm/boot/dts/stih407-b2120.dts1
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi27
-rw-r--r--arch/arm/boot/dts/stih407-pinctrl.dtsi4
-rw-r--r--arch/arm/boot/dts/stih410-b2120.dts1
-rw-r--r--arch/arm/boot/dts/stih418-b2199.dts8
-rw-r--r--arch/arm/boot/dts/stih418-clock.dtsi2
-rw-r--r--arch/arm/boot/dts/stihxxx-b2120.dtsi6
7 files changed, 46 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index 6d93475be554..c8ad905d0309 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -25,6 +25,7 @@
aliases {
ttyAS0 = &sbc_serial0;
+ ethernet0 = &ethernet0;
};
};
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 582154bbe3f3..c944d3a5906d 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -653,5 +653,32 @@
clocks = <&clk_sysin>;
status = "okay";
};
+
+ ethernet0: dwmac@9630000 {
+ device_type = "network";
+ status = "disabled";
+ compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ reg = <0x9630000 0x8000>, <0x80 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ st,syscon = <&syscfg_sbc_reg 0x80>;
+ st,gmac_en;
+ resets = <&softreset STIH407_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+
+ interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
+ <GIC_SPI 99 IRQ_TYPE_NONE>;
+ interrupt-names = "macirq", "eth_wake_irq";
+
+ /* DMA Bus Mode */
+ snps,pbl = <8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>;
+
+ clock-names = "stmmaceth", "sti-ethclk";
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_ETH_PHY>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 8fe542aa1fa4..a538ae52d32b 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -216,9 +216,9 @@
rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
+ rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
+ phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
};
};
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 8af1e73c0532..118ac284fc4b 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -25,6 +25,7 @@
aliases {
ttyAS0 = &sbc_serial0;
+ ethernet0 = &ethernet0;
};
soc {
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index 82eee39ccb31..772d2bb07e5f 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -24,6 +24,7 @@
aliases {
ttyAS0 = &sbc_serial0;
+ ethernet0 = &ethernet0;
};
soc {
@@ -101,5 +102,12 @@
st_dwc3: dwc3@8f94000 {
status = "okay";
};
+
+ ethernet0: dwmac@9630000 {
+ st,tx-retime-src = "clkgen";
+ status = "okay";
+ phy-mode = "rgmii";
+ fixed-link = <0 1 1000 0 0>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e1772465f..ae6d9978ea19 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index ab029f7239b2..ad21a4293a33 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -87,5 +87,11 @@
status = "okay";
};
+ ethernet0: dwmac@9630000 {
+ st,tx-retime-src = "clkgen";
+ status = "okay";
+ phy-mode = "rgmii";
+ fixed-link = <0 1 1000 0 0>;
+ };
};
};

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