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authorHans de Goede <hdegoede@redhat.com>2016-06-28 22:11:14 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-06-29 09:03:13 +0200
commiteee25ab19de632af1ab4d2ac50bfc5006802e664 (patch)
tree6c6b784b7d29f669c85e5e157989a509c87c8fa9
parentb3b630b26ae87a54e2f396b459aab0cd2286fc77 (diff)
ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clocksunxi-fixes-for-4.7
Fix pll3x2 and pll7x2 not having a parent clock, specifically this fixes the kernel turning of pll3 while simplefb is using it when uboot has configured things to use pll3x2 as lcd ch clk parent. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f480051c1f8a..2c34bbbb9570 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -232,6 +232,7 @@
pll3x2: pll3x2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clocks = <&pll3>;
clock-div = <1>;
clock-mult = <2>;
clock-output-names = "pll3-2x";
@@ -273,6 +274,7 @@
pll7x2: pll7x2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clocks = <&pll7>;
clock-div = <1>;
clock-mult = <2>;
clock-output-names = "pll7-2x";

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