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authorChen-Yu Tsai <wens@csie.org>2015-03-25 01:22:08 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-03-25 11:46:41 -0700
commitf1017969661dd33ead5ba7c3f4a0793c6611441a (patch)
treeb4e6aec3ce3765f5c6692abec131768ffa8110bc
parent934fe5f48ae52841f8a5f5e0411147a8ccd171c1 (diff)
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6sunxi-clocks-for-4.1
The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9f31314a9cd7..7e1e2bd189b6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = {
static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data,
- .ndivs = 3,
+ .ndivs = 4,
.div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
{ .fixed = 2 }, /* P, other */
{ .self = 1 }, /* base factor clock, 2x */
+ { .fixed = 4 }, /* pll6 / 4, used as ahb input */
}
};

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