diff options
authorAndreas Färber <afaerber@suse.de>2014-11-06 18:22:10 +0100
committerOlof Johansson <olof@lixom.net>2014-11-08 16:57:44 -0800
commit92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c (patch)
parent5305e4d674ed5ec9bebd11d948affd411594d4cf (diff)
ARM: dts: zynq: Enable PL clocks for Parallella
The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Cc: <stable@vger.kernel.org> # 3.17.x Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
+&clkc {
+ fclk-enable = <0xf>;
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

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