path: root/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
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authorMaciej W. Rozycki <macro@orcam.me.uk>2021-04-22 22:36:12 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2021-04-23 13:40:31 +0200
commit25ab14cbe9d1b66fda44c71a2db7582a31b6f5cd (patch)
tree0f4f4295cf97bf6bb40334a769d766ec99ff90f9 /arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
parent517b322c07e17787fc8a22ca9cede709b6ae9ec0 (diff)
MIPS: Avoid handcoded DIVU in `__div64_32' altogether
Remove the inline asm with a DIVU instruction from `__div64_32' and use plain C code for the intended DIVMOD calculation instead. GCC is smart enough to know that both the quotient and the remainder are calculated with single DIVU, so with ISAs up to R5 the same instruction is actually produced with overall similar code. For R6 compiled code will work, but separate DIVU and MODU instructions will be produced, which are also interlocked, so scalar implementations will likely not perform as well as older ISAs with their asynchronous MD unit. Likely still faster then the generic algorithm though. This removes a compilation error for R6 however where the original DIVU instruction is not supported anymore and the MDU accumulator registers have been removed and consequently GCC complains as to a constraint it cannot find a register for: In file included from ./include/linux/math.h:5, from ./include/linux/kernel.h:13, from mm/page-writeback.c:15: ./include/linux/math64.h: In function 'div_u64_rem': ./arch/mips/include/asm/div64.h:76:17: error: inconsistent operand constraints in an 'asm' 76 | __asm__("divu $0, %z1, %z2" \ | ^~~~~~~ ./include/asm-generic/div64.h:245:25: note: in expansion of macro '__div64_32' 245 | __rem = __div64_32(&(n), __base); \ | ^~~~~~~~~~ ./include/linux/math64.h:91:22: note: in expansion of macro 'do_div' 91 | *remainder = do_div(dividend, divisor); | ^~~~~~ This has passed correctness verification with test_div64 and reduced the module's average execution time down to 1.0404s from 1.0445s with R3400 @40MHz. The module's MIPS I machine code has also shrunk by 12 bytes or 3 instructions. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi')
0 files changed, 0 insertions, 0 deletions

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