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authorJon Mason <jonmason@broadcom.com>2015-10-15 15:48:26 -0400
committerStephen Boyd <sboyd@codeaurora.org>2015-10-21 16:53:15 -0700
commit01b6722fdf65a91d588338e5a1964d57fa2dd590 (patch)
tree604e56f8653928722fae07605c2552d72e3fea57 /drivers/clk/bcm/clk-iproc.h
parent2dfc8a27ecfb3a54cc60376e0e7c4872934008f1 (diff)
clk: iproc: Add PWRCTRL support
Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN. Signed-off-by: Jon Mason <jonmason@broadcom.com> [sboyd@codeaurora.org: Remove useless parentheses] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/bcm/clk-iproc.h')
-rw-r--r--drivers/clk/bcm/clk-iproc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index d834b7abd5c6..ff7bfad48c13 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -49,6 +49,12 @@
#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
/*
+ * Some PLLs use a different way to control clock power, via the PWRDWN bit in
+ * the PLL control register
+ */
+#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
+
+/*
* Parameters for VCO frequency configuration
*
* VCO frequency =

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