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authorSimran Rai <ssimran@broadcom.com>2016-01-26 17:18:39 -0800
committerStephen Boyd <sboyd@codeaurora.org>2016-01-29 16:31:38 -0800
commitbcd8be139803f51834347840349c150bf0e4eb96 (patch)
tree291d7867d7475a73f41cd68f454a4e6348f0c307 /drivers/clk/bcm/clk-iproc.h
parent7eb24279d2094eda074527762629d8146b148a22 (diff)
clk: iproc: Add support for Cygnus audio clocks
This patch adds support for Broadcom Cygnus audio PLL and leaf clocks Signed-off-by: Simran Rai <ssimran@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/bcm/clk-iproc.h')
-rw-r--r--drivers/clk/bcm/clk-iproc.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index 8988de70a98c..febae119f9ef 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -61,6 +61,26 @@
#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
/*
+ * Some PLLs have an additional divide by 2 in master clock calculation;
+ * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
+ * of modified calculations
+ */
+#define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
+
+/*
+ * Some PLLs provide a look up table for the leaf clock frequencies and
+ * auto calculates VCO frequency parameters based on the provided leaf
+ * clock frequencies. They have a user mode that allows the divider
+ * controls to be determined by the user
+ */
+#define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
+
+/*
+ * Some PLLs have an active low reset
+ */
+#define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
+
+/*
* Parameters for VCO frequency configuration
*
* VCO frequency =
@@ -149,6 +169,7 @@ struct iproc_pll_ctrl {
struct iproc_clk_reg_op pdiv;
struct iproc_pll_vco_ctrl vco_ctrl;
struct iproc_clk_reg_op status;
+ struct iproc_clk_reg_op macro_mode;
};
/*

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