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authorJon Mason <jonmason@broadcom.com>2015-10-15 15:48:29 -0400
committerStephen Boyd <sboyd@codeaurora.org>2015-10-21 17:02:57 -0700
commitf713c6bf32092a259d6baf2be24f9c3dbf2462c3 (patch)
tree175ddb6a03c3187d358f50f201f22076fc47db46 /drivers/clk/bcm/clk-iproc.h
parent7968d24107f5a50a11792f8a7f011877e7470dfa (diff)
clk: iproc: Split off dig_filter
The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/bcm/clk-iproc.h')
-rw-r--r--drivers/clk/bcm/clk-iproc.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index ff7bfad48c13..b71c19737efd 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl {
};
/*
- * Control of the PLL reset, with Ki, Kp, and Ka parameters
+ * Control of the PLL reset
*/
struct iproc_pll_reset_ctrl {
unsigned int offset;
unsigned int reset_shift;
unsigned int p_reset_shift;
+};
+
+/*
+ * Control of the Ki, Kp, and Ka parameters
+ */
+struct iproc_pll_dig_filter_ctrl {
+ unsigned int offset;
unsigned int ki_shift;
unsigned int ki_width;
unsigned int kp_shift;
@@ -129,6 +136,7 @@ struct iproc_pll_ctrl {
struct iproc_pll_aon_pwr_ctrl aon;
struct iproc_asiu_gate asiu;
struct iproc_pll_reset_ctrl reset;
+ struct iproc_pll_dig_filter_ctrl dig_filter;
struct iproc_pll_sw_ctrl sw_ctrl;
struct iproc_clk_reg_op ndiv_int;
struct iproc_clk_reg_op ndiv_frac;

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