path: root/drivers/clk/qcom/gdsc.h
diff options
authorRajendra Nayak <rnayak@codeaurora.org>2015-08-06 16:07:44 +0530
committerStephen Boyd <sboyd@codeaurora.org>2015-09-16 15:22:39 -0700
commit014e193ccd197d15b6f7bf6d3d616600091c14ad (patch)
treec076c667c5deb6b94a0b01427e47d81e659fc195 /drivers/clk/qcom/gdsc.h
parent5e5cc241e9c448d1f6e5fdef843ab018a9947d5c (diff)
clk: qcom: gdsc: Add support for Memory RET/OFF
Along with the GDSC power switch, there is additional control to either retain all memory (core and peripheral) within a given powerdomain or to turn them off while the GDSC is powered down. Add support for these by modelling a RET state where all memory is retained and an OFF state where all memory gets turned off. The controls provided are granular enough to be able to support various differnt levels of RET states, like a 'shallow RET' with all memory retained and a 'deep RET' with some memory retained while some others are lost. The current patch does not support this and considers just one RET state where all memory is retained. Futher work, if needed can support multiple different levels of RET state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/gdsc.h')
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index f578a0cce425..0ff251a5523f 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -19,16 +19,29 @@
struct regmap;
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF BIT(0)
+#define PWRSTS_RET BIT(1)
+#define PWRSTS_ON BIT(2)
* struct gdsc - Globally Distributed Switch Controller
* @pd: generic power domain
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
+ * @cxcs: offsets of branch registers to toggle mem/periph bits in
+ * @cxc_count: number of @cxcs
+ * @pwrsts: Possible powerdomain power states
struct gdsc {
struct generic_pm_domain pd;
struct regmap *regmap;
unsigned int gdscr;
+ unsigned int *cxcs;
+ unsigned int cxc_count;
+ const u8 pwrsts;

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