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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2018-01-12 16:48:01 +1100
committerStephen Boyd <sboyd@codeaurora.org>2018-01-26 16:22:48 -0800
commit6671507f0fbd582b4003f837ab791d03ade8e0f4 (patch)
tree87615147b69008ac30cfcff53765d749fc73e979 /drivers/clk/sunxi-ng
parentaccf475a5ece972af58c81e0742035ed90ad41d2 (diff)
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
The USB port 1 clock gate control has an inversed polarity from all the other clock gates in the chip. This makes the aspeed_clk_{enable,disable} functions honor the flag CLK_GATE_SET_TO_DISABLE and set that flag appropriately so it's set for all clocks except USB port 1. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/sunxi-ng')
0 files changed, 0 insertions, 0 deletions

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