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authorLinus Torvalds <torvalds@linux-foundation.org>2018-02-01 16:56:07 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2018-02-01 16:56:07 -0800
commit3879ae653a3e98380fe2daf653338830b7ca0097 (patch)
treea577c4af2ac2747f562aa01dd4f1f3ec550da741 /drivers/clk
parentfe53d1443a146326b49d57fe6336b5c2a725223f (diff)
parentc43a52cfd27b20292d19d924eddfa5ff8dce87e5 (diff)
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "The core framework has a handful of patches this time around, mostly due to the clk rate protection support added by Jerome Brunet. This feature will allow consumers to lock in a certain rate on the output of a clk so that things like audio playback don't hear pops when the clk frequency changes due to shared parent clks changing rates. Currently the clk API doesn't guarantee the rate of a clk stays at the rate you request after clk_set_rate() is called, so this new API will allow drivers to express that requirement. Beyond this, the core got some debugfs pretty printing patches and a couple minor non-critical fixes. Looking outside of the core framework diff we have some new driver additions and the removal of a legacy TI clk driver. Both of these hit high in the dirstat. Also, the removal of the asm-generic/clkdev.h file causes small one-liners in all the architecture Kbuild files. Overall, the driver diff seems to be the normal stuff that comes all the time to fix little problems here and there and to support new hardware. Summary: Core: - Clk rate protection - Symbolic clk flags in debugfs output - Clk registration enabled clks while doing bookkeeping updates New Drivers: - Spreadtrum SC9860 - HiSilicon hi3660 stub - Qualcomm A53 PLL, SPMI clkdiv, and MSM8916 APCS - Amlogic Meson-AXG - ASPEED BMC Removed Drivers: - TI OMAP 3xxx legacy clk (non-DT) support - asm*/clkdev.h got removed (not really a driver) Updates: - Renesas FDP1-0 module clock on R-Car M3-W - Renesas LVDS module clock on R-Car V3M - Misc fixes to pr_err() prints - Qualcomm MSM8916 audio fixes - Qualcomm IPQ8074 rounded out support for more peripherals - Qualcomm Alpha PLL variants - Divider code was using container_of() on bad pointers - Allwinner DE2 clks on H3 - Amlogic minor data fixes and dropping of CLK_IGNORE_UNUSED - Mediatek clk driver compile test support - AT91 PMC clk suspend/resume restoration support - PLL issues fixed on si5351 - Broadcom IProc PLL calculation updates - DVFS support for Armada mvebu CPU clks - Allwinner fixed post-divider support - TI clkctrl fixes and support for newer SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits) clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: fix reentrancy of clk_enable() on UP systems clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: renesas: r8a7796: Add FDP clock clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks clk: Improve flags doc for of_clk_detect_critical() arch: Remove clkdev.h asm-generic from Kbuild clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: Prepare to remove asm-generic/clkdev.h ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Kconfig13
-rw-r--r--drivers/clk/Makefile4
-rw-r--r--drivers/clk/at91/clk-programmable.c2
-rw-r--r--drivers/clk/at91/pmc.c63
-rw-r--r--drivers/clk/at91/pmc.h2
-rw-r--r--drivers/clk/bcm/clk-cygnus.c25
-rw-r--r--drivers/clk/bcm/clk-iproc-pll.c260
-rw-r--r--drivers/clk/bcm/clk-iproc.h5
-rw-r--r--drivers/clk/clk-aspeed.c667
-rw-r--r--drivers/clk/clk-axi-clkgen.c39
-rw-r--r--drivers/clk/clk-divider.c7
-rw-r--r--drivers/clk/clk-qoriq.c9
-rw-r--r--drivers/clk/clk-si5351.c68
-rw-r--r--drivers/clk/clk-stm32f4.c2
-rw-r--r--drivers/clk/clk-stm32h7.c19
-rw-r--r--drivers/clk/clk.c620
-rw-r--r--drivers/clk/clk.h4
-rw-r--r--drivers/clk/clkdev.c2
-rw-r--r--drivers/clk/h8300/clk-div.c4
-rw-r--r--drivers/clk/h8300/clk-h8s2678.c6
-rw-r--r--drivers/clk/hisilicon/Kconfig6
-rw-r--r--drivers/clk/hisilicon/Makefile1
-rw-r--r--drivers/clk/hisilicon/clk-hi3660-stub.c185
-rw-r--r--drivers/clk/hisilicon/clkdivider-hi6220.c2
-rw-r--r--drivers/clk/imx/clk-imx51-imx53.c12
-rw-r--r--drivers/clk/mediatek/Kconfig97
-rw-r--r--drivers/clk/mediatek/Makefile3
-rw-r--r--drivers/clk/mediatek/clk-mtk.h8
-rw-r--r--drivers/clk/meson/Kconfig8
-rw-r--r--drivers/clk/meson/Makefile1
-rw-r--r--drivers/clk/meson/axg.c938
-rw-r--r--drivers/clk/meson/axg.h126
-rw-r--r--drivers/clk/meson/clk-mpll.c2
-rw-r--r--drivers/clk/meson/clkc.h2
-rw-r--r--drivers/clk/meson/gxbb.c132
-rw-r--r--drivers/clk/meson/meson8b.c24
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c317
-rw-r--r--drivers/clk/nxp/clk-lpc32xx.c6
-rw-r--r--drivers/clk/pxa/clk-pxa3xx.c6
-rw-r--r--drivers/clk/qcom/Kconfig30
-rw-r--r--drivers/clk/qcom/Makefile4
-rw-r--r--drivers/clk/qcom/a53-pll.c107
-rw-r--r--drivers/clk/qcom/apcs-msm8916.c138
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c516
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h35
-rw-r--r--drivers/clk/qcom/clk-rcg.h10
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.c31
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.h1
-rw-r--r--drivers/clk/qcom/clk-regmap-mux-div.c231
-rw-r--r--drivers/clk/qcom/clk-regmap-mux-div.h44
-rw-r--r--drivers/clk/qcom/clk-regmap-mux.c6
-rw-r--r--drivers/clk/qcom/clk-regmap-mux.h2
-rw-r--r--drivers/clk/qcom/clk-spmi-pmic-div.c302
-rw-r--r--drivers/clk/qcom/common.h11
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c3752
-rw-r--r--drivers/clk/qcom/gcc-msm8916.c13
-rw-r--r--drivers/clk/qcom/gcc-msm8994.c4
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c4
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c16
-rw-r--r--drivers/clk/renesas/clk-mstp.c2
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a77970-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c2
-rw-r--r--drivers/clk/spear/clk-frac-synth.c2
-rw-r--r--drivers/clk/spear/clk-gpt-synth.c2
-rw-r--r--drivers/clk/sprd/Kconfig14
-rw-r--r--drivers/clk/sprd/Makefile11
-rw-r--r--drivers/clk/sprd/common.c96
-rw-r--r--drivers/clk/sprd/common.h38
-rw-r--r--drivers/clk/sprd/composite.c60
-rw-r--r--drivers/clk/sprd/composite.h51
-rw-r--r--drivers/clk/sprd/div.c91
-rw-r--r--drivers/clk/sprd/div.h75
-rw-r--r--drivers/clk/sprd/gate.c111
-rw-r--r--drivers/clk/sprd/gate.h59
-rw-r--r--drivers/clk/sprd/mux.c76
-rw-r--r--drivers/clk/sprd/mux.h74
-rw-r--r--drivers/clk/sprd/pll.c266
-rw-r--r--drivers/clk/sprd/pll.h108
-rw-r--r--drivers/clk/sprd/sc9860-clk.c1974
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-a64.c57
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a83t.c22
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-de2.c53
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h29
-rw-r--r--drivers/clk/sunxi-ng/ccu_div.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu_mp.c20
-rw-r--r--drivers/clk/sunxi-ng/ccu_mp.h24
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.c50
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h2
-rw-r--r--drivers/clk/sunxi/clk-factors.c26
-rw-r--r--drivers/clk/sunxi/clk-factors.h4
-rw-r--r--drivers/clk/sunxi/clk-mod0.c9
-rw-r--r--drivers/clk/sunxi/clk-sun8i-apb0.c5
-rw-r--r--drivers/clk/sunxi/clk-sun8i-mbus.c7
-rw-r--r--drivers/clk/sunxi/clk-sun9i-core.c9
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c36
-rw-r--r--drivers/clk/ti/Makefile4
-rw-r--r--drivers/clk/ti/clk-3xxx-legacy.c4656
-rw-r--r--drivers/clk/ti/clk.c135
-rw-r--r--drivers/clk/ti/clock.h68
-rw-r--r--drivers/clk/ti/composite.c45
-rw-r--r--drivers/clk/ti/dpll.c90
-rw-r--r--drivers/clk/ti/gate.c48
-rw-r--r--drivers/clk/ti/interface.c32
-rw-r--r--drivers/clk/zte/clk.h18
105 files changed, 11752 insertions, 5767 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1c4e1aa6767e..98ce9fc6e6c0 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI
This driver supports the SoC clocks on the Cortina Systems Gemini
platform, also known as SL3516 or CS3516.
+config COMMON_CLK_ASPEED
+ bool "Clock driver for Aspeed BMC SoCs"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ default ARCH_ASPEED
+ select MFD_SYSCON
+ select RESET_CONTROLLER
+ ---help---
+ This driver supports the SoC clocks on the Aspeed BMC platforms.
+
+ The G4 and G5 series, including the ast2400 and ast2500, are supported
+ by this driver.
+
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE || COMPILE_TEST
@@ -236,6 +248,7 @@ source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/samsung/Kconfig"
+source "drivers/clk/sprd/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f7f761b02bed..71ec41e6364f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
+obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
@@ -67,7 +68,7 @@ obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_MACH_INGENIC) += ingenic/
obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+obj-y += mediatek/
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/
obj-$(CONFIG_MACH_PIC32) += microchip/
ifeq ($(CONFIG_COMMON_CLK), y)
@@ -85,6 +86,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_ARCH_SIRF) += sirf/
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
+obj-$(CONFIG_ARCH_SPRD) += sprd/
obj-$(CONFIG_ARCH_STI) += st/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 85a449cf61e3..0e6aab1252fc 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -204,6 +204,8 @@ at91_clk_register_programmable(struct regmap *regmap,
if (ret) {
kfree(prog);
hw = ERR_PTR(ret);
+ } else {
+ pmc_register_pck(id);
}
return hw;
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 775af473fe11..1fa27f4ea538 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -22,6 +22,7 @@
#include "pmc.h"
#define PMC_MAX_IDS 128
+#define PMC_MAX_PCKS 8
int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk_range *range)
@@ -50,6 +51,7 @@ EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
static struct regmap *pmcreg;
static u8 registered_ids[PMC_MAX_IDS];
+static u8 registered_pcks[PMC_MAX_PCKS];
static struct
{
@@ -66,8 +68,13 @@ static struct
u32 pcr[PMC_MAX_IDS];
u32 audio_pll0;
u32 audio_pll1;
+ u32 pckr[PMC_MAX_PCKS];
} pmc_cache;
+/*
+ * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
+ * without alteration in the table, and 0 is for unused clocks.
+ */
void pmc_register_id(u8 id)
{
int i;
@@ -82,11 +89,30 @@ void pmc_register_id(u8 id)
}
}
+/*
+ * As Programmable Clock 0 is valid on AT91 chips, there is an offset
+ * of 1 between the stored value and the real clock ID.
+ */
+void pmc_register_pck(u8 pck)
+{
+ int i;
+
+ for (i = 0; i < PMC_MAX_PCKS; i++) {
+ if (registered_pcks[i] == 0) {
+ registered_pcks[i] = pck + 1;
+ break;
+ }
+ if (registered_pcks[i] == (pck + 1))
+ break;
+ }
+}
+
static int pmc_suspend(void)
{
int i;
+ u8 num;
- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.scsr);
+ regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
@@ -103,14 +129,29 @@ static int pmc_suspend(void)
regmap_read(pmcreg, AT91_PMC_PCR,
&pmc_cache.pcr[registered_ids[i]]);
}
+ for (i = 0; registered_pcks[i]; i++) {
+ num = registered_pcks[i] - 1;
+ regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
+ }
return 0;
}
+static bool pmc_ready(unsigned int mask)
+{
+ unsigned int status;
+
+ regmap_read(pmcreg, AT91_PMC_SR, &status);
+
+ return ((status & mask) == mask) ? 1 : 0;
+}
+
static void pmc_resume(void)
{
- int i, ret = 0;
+ int i;
+ u8 num;
u32 tmp;
+ u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
if (pmc_cache.mckr != tmp)
@@ -119,7 +160,7 @@ static void pmc_resume(void)
if (pmc_cache.pllar != tmp)
pr_warn("PLLAR was not configured properly by the firmware\n");
- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.scsr);
+ regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
@@ -133,14 +174,16 @@ static void pmc_resume(void)
pmc_cache.pcr[registered_ids[i]] |
AT91_PMC_PCR_CMD);
}
-
- if (pmc_cache.uckr & AT91_PMC_UPLLEN) {
- ret = regmap_read_poll_timeout(pmcreg, AT91_PMC_SR, tmp,
- !(tmp & AT91_PMC_LOCKU),
- 10, 5000);
- if (ret)
- pr_crit("USB PLL didn't lock when resuming\n");
+ for (i = 0; registered_pcks[i]; i++) {
+ num = registered_pcks[i] - 1;
+ regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
}
+
+ if (pmc_cache.uckr & AT91_PMC_UPLLEN)
+ mask |= AT91_PMC_LOCKU;
+
+ while (!pmc_ready(mask))
+ cpu_relax();
}
static struct syscore_ops pmc_syscore_ops = {
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 858e8ef7e8db..d22b1fa9ecdc 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -31,8 +31,10 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname,
#ifdef CONFIG_PM
void pmc_register_id(u8 id);
+void pmc_register_pck(u8 pck);
#else
static inline void pmc_register_id(u8 id) {}
+static inline void pmc_register_pck(u8 pck) {}
#endif
#endif /* __PMC_H_ */
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index 464fdc4bc66b..b8d073e4855f 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -269,23 +269,10 @@ static void __init cygnus_asiu_init(struct device_node *node)
}
CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
-/*
- * AUDIO PLL VCO frequency parameter table
- *
- * PLL output frequency = ((ndiv_int + ndiv_frac / 2^20) *
- * (parent clock rate / pdiv)
- *
- * On Cygnus, parent is the 25MHz oscillator
- */
-static const struct iproc_pll_vco_param audiopll_vco_params[] = {
- /* rate (Hz) ndiv_int ndiv_frac pdiv */
- { 1354750204UL, 54, 199238, 1 },
- { 1769470191UL, 70, 816639, 1 },
-};
-
static const struct iproc_pll_ctrl audiopll = {
.flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC |
- IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW,
+ IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW |
+ IPROC_CLK_PLL_CALC_PARAM,
.reset = RESET_VAL(0x5c, 0, 1),
.dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),
.sw_ctrl = SW_CTRL_VAL(0x4, 0),
@@ -300,8 +287,7 @@ static const struct iproc_pll_ctrl audiopll = {
static const struct iproc_clk_ctrl audiopll_clk[] = {
[BCM_CYGNUS_AUDIOPLL_CH0] = {
.channel = BCM_CYGNUS_AUDIOPLL_CH0,
- .flags = IPROC_CLK_AON |
- IPROC_CLK_MCLK_DIV_BY_2,
+ .flags = IPROC_CLK_AON | IPROC_CLK_MCLK_DIV_BY_2,
.enable = ENABLE_VAL(0x14, 8, 10, 9),
.mdiv = REG_VAL(0x14, 0, 8),
},
@@ -321,9 +307,8 @@ static const struct iproc_clk_ctrl audiopll_clk[] = {
static void __init cygnus_audiopll_clk_init(struct device_node *node)
{
- iproc_pll_clk_setup(node, &audiopll, audiopll_vco_params,
- ARRAY_SIZE(audiopll_vco_params), audiopll_clk,
- ARRAY_SIZE(audiopll_clk));
+ iproc_pll_clk_setup(node, &audiopll, NULL, 0,
+ audiopll_clk, ARRAY_SIZE(audiopll_clk));
}
CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",
cygnus_audiopll_clk_init);
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 375d8dd80d45..43a58ae5a89d 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -69,16 +69,6 @@ enum vco_freq_range {
VCO_MAX = 4000000000U,
};
-struct iproc_pll;
-
-struct iproc_clk {
- struct clk_hw hw;
- const char *name;
- struct iproc_pll *pll;
- unsigned long rate;
- const struct iproc_clk_ctrl *ctrl;
-};
-
struct iproc_pll {
void __iomem *status_base;
void __iomem *control_base;
@@ -88,13 +78,49 @@ struct iproc_pll {
const struct iproc_pll_ctrl *ctrl;
const struct iproc_pll_vco_param *vco_param;
unsigned int num_vco_entries;
+};
- struct clk_hw_onecell_data *clk_data;
- struct iproc_clk *clks;
+struct iproc_clk {
+ struct clk_hw hw;
+ struct iproc_pll *pll;
+ const struct iproc_clk_ctrl *ctrl;
};
#define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw)
+static int pll_calc_param(unsigned long target_rate,
+ unsigned long parent_rate,
+ struct iproc_pll_vco_param *vco_out)
+{
+ u64 ndiv_int, ndiv_frac, residual;
+
+ ndiv_int = target_rate / parent_rate;
+
+ if (!ndiv_int || (ndiv_int > 255))
+ return -EINVAL;
+
+ residual = target_rate - (ndiv_int * parent_rate);
+ residual <<= 20;
+
+ /*
+ * Add half of the divisor so the result will be rounded to closest
+ * instead of rounded down.
+ */
+ residual += (parent_rate / 2);
+ ndiv_frac = div64_u64((u64)residual, (u64)parent_rate);
+
+ vco_out->ndiv_int = ndiv_int;
+ vco_out->ndiv_frac = ndiv_frac;
+ vco_out->pdiv = 1;
+
+ vco_out->rate = vco_out->ndiv_int * parent_rate;
+ residual = (u64)vco_out->ndiv_frac * (u64)parent_rate;
+ residual >>= 20;
+ vco_out->rate += residual;
+
+ return 0;
+}
+
/*
* Based on the target frequency, find a match from the VCO frequency parameter
* table and return its index
@@ -252,17 +278,51 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
iproc_pll_write(pll, pll->control_base, reset->offset, val);
}
-static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
+/*
+ * Determines if the change to be applied to the PLL is minor (just an update
+ * or the fractional divider). If so, then we can avoid going through a
+ * disruptive reset and lock sequence.
+ */
+static bool pll_fractional_change_only(struct iproc_pll *pll,
+ struct iproc_pll_vco_param *vco)
+{
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ u32 val;
+ u32 ndiv_int;
+ unsigned int pdiv;
+
+ /* PLL needs to be locked */
+ val = readl(pll->status_base + ctrl->status.offset);
+ if ((val & (1 << ctrl->status.shift)) == 0)
+ return false;
+
+ val = readl(pll->control_base + ctrl->ndiv_int.offset);
+ ndiv_int = (val >> ctrl->ndiv_int.shift) &
+ bit_mask(ctrl->ndiv_int.width);
+
+ if (ndiv_int != vco->ndiv_int)
+ return false;
+
+ val = readl(pll->control_base + ctrl->pdiv.offset);
+ pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
+
+ if (pdiv != vco->pdiv)
+ return false;
+
+ return true;
+}
+
+static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco,
unsigned long parent_rate)
{
struct iproc_pll *pll = clk->pll;
- const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index];
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
int ka = 0, ki, kp, ret;
unsigned long rate = vco->rate;
u32 val;
enum kp_band kp_index;
unsigned long ref_freq;
+ const char *clk_name = clk_hw_get_name(&clk->hw);
/*
* reference frequency = parent frequency / PDIV
@@ -285,22 +345,35 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
kp_index = KP_BAND_HIGH_HIGH;
} else {
pr_err("%s: pll: %s has invalid rate: %lu\n", __func__,
- clk->name, rate);
+ clk_name, rate);
return -EINVAL;
}
kp = get_kp(ref_freq, kp_index);
if (kp < 0) {
- pr_err("%s: pll: %s has invalid kp\n", __func__, clk->name);
+ pr_err("%s: pll: %s has invalid kp\n", __func__, clk_name);
return kp;
}
ret = __pll_enable(pll);
if (ret) {
- pr_err("%s: pll: %s fails to enable\n", __func__, clk->name);
+ pr_err("%s: pll: %s fails to enable\n", __func__, clk_name);
return ret;
}
+ if (pll_fractional_change_only(clk->pll, vco)) {
+ /* program fractional part of NDIV */
+ if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
+ val = readl(pll->control_base + ctrl->ndiv_frac.offset);
+ val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
+ ctrl->ndiv_frac.shift);
+ val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
+ iproc_pll_write(pll, pll->control_base,
+ ctrl->ndiv_frac.offset, val);
+ return 0;
+ }
+ }
+
/* put PLL in reset */
__pll_put_in_reset(pll);
@@ -354,7 +427,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
ret = pll_wait_for_lock(pll);
if (ret < 0) {
- pr_err("%s: pll: %s failed to lock\n", __func__, clk->name);
+ pr_err("%s: pll: %s failed to lock\n", __func__, clk_name);
return ret;
}
@@ -390,16 +463,15 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
u32 val;
u64 ndiv, ndiv_int, ndiv_frac;
unsigned int pdiv;
+ unsigned long rate;
if (parent_rate == 0)
return 0;
/* PLL needs to be locked */
val = readl(pll->status_base + ctrl->status.offset);
- if ((val & (1 << ctrl->status.shift)) == 0) {
- clk->rate = 0;
+ if ((val & (1 << ctrl->status.shift)) == 0)
return 0;
- }
/*
* PLL output frequency =
@@ -421,35 +493,60 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
val = readl(pll->control_base + ctrl->pdiv.offset);
pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
- clk->rate = (ndiv * parent_rate) >> 20;
+ rate = (ndiv * parent_rate) >> 20;
if (pdiv == 0)
- clk->rate *= 2;
+ rate *= 2;
else
- clk->rate /= pdiv;
+ rate /= pdiv;
- return clk->rate;
+ return rate;
}
-static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int iproc_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- unsigned i;
+ unsigned int i;
struct iproc_clk *clk = to_iproc_clk(hw);
struct iproc_pll *pll = clk->pll;
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ unsigned long diff, best_diff;
+ unsigned int best_idx = 0;
+ int ret;
+
+ if (req->rate == 0 || req->best_parent_rate == 0)
+ return -EINVAL;
+
+ if (ctrl->flags & IPROC_CLK_PLL_CALC_PARAM) {
+ struct iproc_pll_vco_param vco_param;
- if (rate == 0 || *parent_rate == 0 || !pll->vco_param)
+ ret = pll_calc_param(req->rate, req->best_parent_rate,
+ &vco_param);
+ if (ret)
+ return ret;
+
+ req->rate = vco_param.rate;
+ return 0;
+ }
+
+ if (!pll->vco_param)
return -EINVAL;
+ best_diff = ULONG_MAX;
for (i = 0; i < pll->num_vco_entries; i++) {
- if (rate <= pll->vco_param[i].rate)
+ diff = abs(req->rate - pll->vco_param[i].rate);
+ if (diff <= best_diff) {
+ best_diff = diff;
+ best_idx = i;
+ }
+ /* break now if perfect match */
+ if (diff == 0)
break;
}
- if (i == pll->num_vco_entries)
- i--;
+ req->rate = pll->vco_param[best_idx].rate;
- return pll->vco_param[i].rate;
+ return 0;
}
static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -457,13 +554,23 @@ static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct iproc_clk *clk = to_iproc_clk(hw);
struct iproc_pll *pll = clk->pll;
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ struct iproc_pll_vco_param vco_param;
int rate_index, ret;
- rate_index = pll_get_rate_index(pll, rate);
- if (rate_index < 0)
- return rate_index;
+ if (ctrl->flags & IPROC_CLK_PLL_CALC_PARAM) {
+ ret = pll_calc_param(rate, parent_rate, &vco_param);
+ if (ret)
+ return ret;
+ } else {
+ rate_index = pll_get_rate_index(pll, rate);
+ if (rate_index < 0)
+ return rate_index;
- ret = pll_set_rate(clk, rate_index, parent_rate);
+ vco_param = pll->vco_param[rate_index];
+ }
+
+ ret = pll_set_rate(clk, &vco_param, parent_rate);
return ret;
}
@@ -471,7 +578,7 @@ static const struct clk_ops iproc_pll_ops = {
.enable = iproc_pll_enable,
.disable = iproc_pll_disable,
.recalc_rate = iproc_pll_recalc_rate,
- .round_rate = iproc_pll_round_rate,
+ .determine_rate = iproc_pll_determine_rate,
.set_rate = iproc_pll_set_rate,
};
@@ -518,6 +625,7 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
struct iproc_pll *pll = clk->pll;
u32 val;
unsigned int mdiv;
+ unsigned long rate;
if (parent_rate == 0)
return 0;
@@ -528,32 +636,33 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
mdiv = 256;
if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)
- clk->rate = parent_rate / (mdiv * 2);
+ rate = parent_rate / (mdiv * 2);
else
- clk->rate = parent_rate / mdiv;
+ rate = parent_rate / mdiv;
- return clk->rate;
+ return rate;
}
-static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int iproc_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- unsigned int div;
+ unsigned int bestdiv;
- if (rate == 0 || *parent_rate == 0)
+ if (req->rate == 0)
return -EINVAL;
+ if (req->rate == req->best_parent_rate)
+ return 0;
- if (rate == *parent_rate)
- return *parent_rate;
+ bestdiv = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
+ if (bestdiv < 2)
+ req->rate = req->best_parent_rate;
- div = DIV_ROUND_UP(*parent_rate, rate);
- if (div < 2)
- return *parent_rate;
+ if (bestdiv > 256)
+ bestdiv = 256;
- if (div > 256)
- div = 256;
+ req->rate = req->best_parent_rate / bestdiv;
- return *parent_rate / div;
+ return 0;
}
static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -568,10 +677,10 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
if (rate == 0 || parent_rate == 0)
return -EINVAL;
+ div = DIV_ROUND_CLOSEST(parent_rate, rate);
if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)
- div = DIV_ROUND_UP(parent_rate, rate * 2);
- else
- div = DIV_ROUND_UP(parent_rate, rate);
+ div /= 2;
+
if (div > 256)
return -EINVAL;
@@ -583,10 +692,6 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
val |= div << ctrl->mdiv.shift;
}
iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val);
- if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)
- clk->rate = parent_rate / (div * 2);
- else
- clk->rate = parent_rate / div;
return 0;
}
@@ -595,7 +700,7 @@ static const struct clk_ops iproc_clk_ops = {
.enable = iproc_clk_enable,
.disable = iproc_clk_disable,
.recalc_rate = iproc_clk_recalc_rate,
- .round_rate = iproc_clk_round_rate,
+ .determine_rate = iproc_clk_determine_rate,
.set_rate = iproc_clk_set_rate,
};
@@ -629,6 +734,8 @@ void iproc_pll_clk_setup(struct device_node *node,
struct iproc_clk *iclk;
struct clk_init_data init;
const char *parent_name;
+ struct iproc_clk *iclk_array;
+ struct clk_hw_onecell_data *clk_data;
if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl))
return;
@@ -637,14 +744,14 @@ void iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(!pll))
return;
- pll->clk_data = kzalloc(sizeof(*pll->clk_data->hws) * num_clks +
- sizeof(*pll->clk_data), GFP_KERNEL);
- if (WARN_ON(!pll->clk_data))
+ clk_data = kzalloc(sizeof(*clk_data->hws) * num_clks +
+ sizeof(*clk_data), GFP_KERNEL);
+ if (WARN_ON(!clk_data))
goto err_clk_data;
- pll->clk_data->num = num_clks;
+ clk_data->num = num_clks;
- pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL);
- if (WARN_ON(!pll->clks))
+ iclk_array = kcalloc(num_clks, sizeof(struct iproc_clk), GFP_KERNEL);
+ if (WARN_ON(!iclk_array))
goto err_clks;
pll->control_base = of_iomap(node, 0);
@@ -674,9 +781,8 @@ void iproc_pll_clk_setup(struct device_node *node,
/* initialize and register the PLL itself */
pll->ctrl = pll_ctrl;
- iclk = &pll->clks[0];
+ iclk = &iclk_array[0];
iclk->pll = pll;
- iclk->name = node->name;
init.name = node->name;
init.ops = &iproc_pll_ops;
@@ -697,7 +803,7 @@ void iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(ret))
goto err_pll_register;
- pll->clk_data->hws[0] = &iclk->hw;
+ clk_data->hws[0] = &iclk->hw;
/* now initialize and register all leaf clocks */
for (i = 1; i < num_clks; i++) {
@@ -711,8 +817,7 @@ void iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(ret))
goto err_clk_register;
- iclk = &pll->clks[i];
- iclk->name = clk_name;
+ iclk = &iclk_array[i];
iclk->pll = pll;
iclk->ctrl = &clk_ctrl[i];
@@ -727,11 +832,10 @@ void iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(ret))
goto err_clk_register;
- pll->clk_data->hws[i] = &iclk->hw;
+ clk_data->hws[i] = &iclk->hw;
}
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- pll->clk_data);
+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (WARN_ON(ret))
goto err_clk_register;
@@ -739,7 +843,7 @@ void iproc_pll_clk_setup(struct device_node *node,
err_clk_register:
while (--i >= 0)
- clk_hw_unregister(pll->clk_data->hws[i]);
+ clk_hw_unregister(clk_data->hws[i]);
err_pll_register:
if (pll->status_base != pll->control_base)
@@ -756,10 +860,10 @@ err_asiu_iomap:
iounmap(pll->control_base);
err_pll_iomap:
- kfree(pll->clks);
+ kfree(iclk_array);
err_clks:
- kfree(pll->clk_data);
+ kfree(clk_data);
err_clk_data:
kfree(pll);
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index 2148b4ea9f28..a48ddd3e0b28 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -81,6 +81,11 @@
#define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
/*
+ * Calculate the PLL parameters are runtime, instead of using table
+ */
+#define IPROC_CLK_PLL_CALC_PARAM BIT(10)
+
+/*
* Parameters for VCO frequency configuration
*
* VCO frequency =
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
new file mode 100644
index 000000000000..9f7f931d6b2f
--- /dev/null
+++ b/drivers/clk/clk-aspeed.c
@@ -0,0 +1,667 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define pr_fmt(fmt) "clk-aspeed: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/aspeed-clock.h>
+
+#define ASPEED_NUM_CLKS 35
+
+#define ASPEED_RESET_CTRL 0x04
+#define ASPEED_CLK_SELECTION 0x08
+#define ASPEED_CLK_STOP_CTRL 0x0c
+#define ASPEED_MPLL_PARAM 0x20
+#define ASPEED_HPLL_PARAM 0x24
+#define AST2500_HPLL_BYPASS_EN BIT(20)
+#define AST2400_HPLL_STRAPPED BIT(18)
+#define AST2400_HPLL_BYPASS_EN BIT(17)
+#define ASPEED_MISC_CTRL 0x2c
+#define UART_DIV13_EN BIT(12)
+#define ASPEED_STRAP 0x70
+#define CLKIN_25MHZ_EN BIT(23)
+#define AST2400_CLK_SOURCE_SEL BIT(18)
+#define ASPEED_CLK_SELECTION_2 0xd8
+
+/* Globally visible clocks */
+static DEFINE_SPINLOCK(aspeed_clk_lock);
+
+/* Keeps track of all clocks */
+static struct clk_hw_onecell_data *aspeed_clk_data;
+
+static void __iomem *scu_base;
+
+/**
+ * struct aspeed_gate_data - Aspeed gated clocks
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @name: the clock name
+ * @parent_name: the name of the parent clock
+ * @flags: standard clock framework flags
+ */
+struct aspeed_gate_data {
+ u8 clock_idx;
+ s8 reset_idx;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+};
+
+/**
+ * struct aspeed_clk_gate - Aspeed specific clk_gate structure
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling gate
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ *
+ * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
+ * This modified version of clk_gate allows an optional reset bit to be
+ * specified.
+ */
+struct aspeed_clk_gate {
+ struct clk_hw hw;
+ struct regmap *map;
+ u8 clock_idx;
+ s8 reset_idx;
+ u8 flags;
+ spinlock_t *lock;
+};
+
+#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
+
+/* TODO: ask Aspeed about the actual parent data */
+static const struct aspeed_gate_data aspeed_gates[] = {
+ /* clk rst name parent flags */
+ [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
+ [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
+ [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
+ [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
+ [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
+ [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
+ [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
+ [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
+ [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
+ [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
+ [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
+ [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
+ [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
+ [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
+ [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
+ [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
+ [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
+ [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
+ [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
+ [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
+ [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
+ [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
+ [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
+ [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
+};
+
+static const struct clk_div_table ast2500_mac_div_table[] = {
+ { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
+ { 0x1, 4 },
+ { 0x2, 6 },
+ { 0x3, 8 },
+ { 0x4, 10 },
+ { 0x5, 12 },
+ { 0x6, 14 },
+ { 0x7, 16 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2400_div_table[] = {
+ { 0x0, 2 },
+ { 0x1, 4 },
+ { 0x2, 6 },
+ { 0x3, 8 },
+ { 0x4, 10 },
+ { 0x5, 12 },
+ { 0x6, 14 },
+ { 0x7, 16 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2500_div_table[] = {
+ { 0x0, 4 },
+ { 0x1, 8 },
+ { 0x2, 12 },
+ { 0x3, 16 },
+ { 0x4, 20 },
+ { 0x5, 24 },
+ { 0x6, 28 },
+ { 0x7, 32 },
+ { 0 }
+};
+
+static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & AST2400_HPLL_BYPASS_EN) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
+ u32 n = (val >> 5) & 0x3f;
+ u32 od = (val >> 4) & 0x1;
+ u32 d = val & 0xf;
+
+ mult = (2 - od) * (n + 2);
+ div = d + 1;
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
+static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & AST2500_HPLL_BYPASS_EN) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
+ u32 p = (val >> 13) & 0x3f;
+ u32 m = (val >> 5) & 0xff;
+ u32 n = val & 0x1f;
+
+ mult = (m + 1) / (n + 1);
+ div = p + 1;
+ }
+
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+}
+
+struct aspeed_clk_soc_data {
+ const struct clk_div_table *div_table;
+ const struct clk_div_table *mac_div_table;
+ struct clk_hw *(*calc_pll)(const char *name, u32 val);
+};
+
+static const struct aspeed_clk_soc_data ast2500_data = {
+ .div_table = ast2500_div_table,
+ .mac_div_table = ast2500_mac_div_table,
+ .calc_pll = aspeed_ast2500_calc_pll,
+};
+
+static const struct aspeed_clk_soc_data ast2400_data = {
+ .div_table = ast2400_div_table,
+ .mac_div_table = ast2400_div_table,
+ .calc_pll = aspeed_ast2400_calc_pll,
+};
+
+static int aspeed_clk_enable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = BIT(gate->clock_idx);
+ u32 rst = BIT(gate->reset_idx);
+ u32 enval;
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ if (gate->reset_idx >= 0) {
+ /* Put IP in reset */
+ regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
+
+ /* Delay 100us */
+ udelay(100);
+ }
+
+ /* Enable clock */
+ enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
+ regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
+
+ if (gate->reset_idx >= 0) {
+ /* A delay of 10ms is specified by the ASPEED docs */
+ mdelay(10);
+
+ /* Take IP out of reset */
+ regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
+ }
+
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ return 0;
+}
+
+static void aspeed_clk_disable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = BIT(gate->clock_idx);
+ u32 enval;
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
+ regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
+
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int aspeed_clk_is_enabled(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ u32 clk = BIT(gate->clock_idx);
+ u32 reg;
+
+ regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
+
+ return (reg & clk) ? 0 : 1;
+}
+
+static const struct clk_ops aspeed_clk_gate_ops = {
+ .enable = aspeed_clk_enable,
+ .disable = aspeed_clk_disable,
+ .is_enabled = aspeed_clk_is_enabled,
+};
+
+/**
+ * struct aspeed_reset - Aspeed reset controller
+ * @map: regmap to access the containing system controller
+ * @rcdev: reset controller device
+ */
+struct aspeed_reset {
+ struct regmap *map;
+ struct reset_controller_dev rcdev;
+};
+
+#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
+
+static const u8 aspeed_resets[] = {
+ [ASPEED_RESET_XDMA] = 25,
+ [ASPEED_RESET_MCTP] = 24,
+ [ASPEED_RESET_ADC] = 23,
+ [ASPEED_RESET_JTAG_MASTER] = 22,
+ [ASPEED_RESET_MIC] = 18,
+ [ASPEED_RESET_PWM] = 9,
+ [ASPEED_RESET_PCIVGA] = 8,
+ [ASPEED_RESET_I2C] = 2,
+ [ASPEED_RESET_AHB] = 1,
+};
+
+static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = BIT(aspeed_resets[id]);
+
+ return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
+}
+
+static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = BIT(aspeed_resets[id]);
+
+ return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
+}
+
+static int aspeed_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 val, rst = BIT(aspeed_resets[id]);
+ int ret;
+
+ ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & rst);
+}
+
+static const struct reset_control_ops aspeed_reset_ops = {
+ .assert = aspeed_reset_assert,
+ .deassert = aspeed_reset_deassert,
+ .status = aspeed_reset_status,
+};
+
+static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ struct regmap *map, u8 clock_idx, u8 reset_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct aspeed_clk_gate *gate;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &aspeed_clk_gate_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ gate->map = map;
+ gate->clock_idx = clock_idx;
+ gate->reset_idx = reset_idx;
+ gate->flags = clk_gate_flags;
+ gate->lock = lock;
+ gate->hw.init = &init;
+
+ hw = &gate->hw;
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(gate);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
+static int aspeed_clk_probe(struct platform_device *pdev)
+{
+ const struct aspeed_clk_soc_data *soc_data;
+ struct device *dev = &pdev->dev;
+ struct aspeed_reset *ar;
+ struct regmap *map;
+ struct clk_hw *hw;
+ u32 val, rate;
+ int i, ret;
+
+ map = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(map)) {
+ dev_err(dev, "no syscon regmap\n");
+ return PTR_ERR(map);
+ }
+
+ ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
+ if (!ar)
+ return -ENOMEM;
+
+ ar->map = map;
+ ar->rcdev.owner = THIS_MODULE;
+ ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
+ ar->rcdev.ops = &aspeed_reset_ops;
+ ar->rcdev.of_node = dev->of_node;
+
+ ret = devm_reset_controller_register(dev, &ar->rcdev);
+ if (ret) {
+ dev_err(dev, "could not register reset controller\n");
+ return ret;
+ }
+
+ /* SoC generations share common layouts but have different divisors */
+ soc_data = of_device_get_match_data(dev);
+ if (!soc_data) {
+ dev_err(dev, "no match data for platform\n");
+ return -EINVAL;
+ }
+
+ /* UART clock div13 setting */
+ regmap_read(map, ASPEED_MISC_CTRL, &val);
+ if (val & UART_DIV13_EN)
+ rate = 24000000 / 13;
+ else
+ rate = 24000000;
+ /* TODO: Find the parent data for the uart clock */
+ hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
+
+ /*
+ * Memory controller (M-PLL) PLL. This clock is configured by the
+ * bootloader, and is exposed to Linux as a read-only clock rate.
+ */
+ regmap_read(map, ASPEED_MPLL_PARAM, &val);
+ hw = soc_data->calc_pll("mpll", val);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
+
+ /* SD/SDIO clock divider (TODO: There's a gate too) */
+ hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
+ scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
+ soc_data->div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
+
+ /* MAC AHB bus clock divider */
+ hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
+ scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
+ soc_data->mac_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
+
+ /* LPC Host (LHCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
+ scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
+ soc_data->div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
+
+ /* P-Bus (BCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
+ scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
+ soc_data->div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
+
+ /*
+ * TODO: There are a number of clocks that not included in this driver
+ * as more information is required:
+ * D2-PLL
+ * D-PLL
+ * YCLK
+ * RGMII
+ * RMII
+ * UART[1..5] clock source mux
+ * Video Engine (ECLK) mux and clock divider
+ */
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
+ const struct aspeed_gate_data *gd = &aspeed_gates[i];
+ u32 gate_flags;
+
+ /* Special case: the USB port 1 clock (bit 14) is always
+ * working the opposite way from the other ones.
+ */
+ gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
+ hw = aspeed_clk_hw_register_gate(dev,
+ gd->name,
+ gd->parent_name,
+ gd->flags,
+ map,
+ gd->clock_idx,
+ gd->reset_idx,
+ gate_flags,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[i] = hw;
+ }
+
+ return 0;
+};
+
+static const struct of_device_id aspeed_clk_dt_ids[] = {
+ { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
+ { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
+ { }
+};
+
+static struct platform_driver aspeed_clk_driver = {
+ .probe = aspeed_clk_probe,
+ .driver = {
+ .name = "aspeed-clk",
+ .of_match_table = aspeed_clk_dt_ids,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(aspeed_clk_driver);
+
+static void __init aspeed_ast2400_cc(struct regmap *map)
+{
+ struct clk_hw *hw;
+ u32 val, freq, div;
+
+ /*
+ * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
+ * strapping
+ */
+ regmap_read(map, ASPEED_STRAP, &val);
+ if (val & CLKIN_25MHZ_EN)
+ freq = 25000000;
+ else if (val & AST2400_CLK_SOURCE_SEL)
+ freq = 48000000;
+ else
+ freq = 24000000;
+ hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
+ pr_debug("clkin @%u MHz\n", freq / 1000000);
+
+ /*
+ * High-speed PLL clock derived from the crystal. This the CPU clock,
+ * and we assume that it is enabled
+ */
+ regmap_read(map, ASPEED_HPLL_PARAM, &val);
+ WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
+ aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);
+
+ /*
+ * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
+ * 00: Select CPU:AHB = 1:1
+ * 01: Select CPU:AHB = 2:1
+ * 10: Select CPU:AHB = 4:1
+ * 11: Select CPU:AHB = 3:1
+ */
+ regmap_read(map, ASPEED_STRAP, &val);
+ val = (val >> 10) & 0x3;
+ div = val + 1;
+ if (div == 3)
+ div = 4;
+ else if (div == 4)
+ div = 3;
+ hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
+ aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
+
+ /* APB clock clock selection register SCU08 (aka PCLK) */
+ hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
+ scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
+ ast2400_div_table,
+ &aspeed_clk_lock);
+ aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
+}
+
+static void __init aspeed_ast2500_cc(struct regmap *map)
+{
+ struct clk_hw *hw;
+ u32 val, freq, div;
+
+ /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
+ regmap_read(map, ASPEED_STRAP, &val);
+ if (val & CLKIN_25MHZ_EN)
+ freq = 25000000;
+ else
+ freq = 24000000;
+ hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
+ pr_debug("clkin @%u MHz\n", freq / 1000000);
+
+ /*
+ * High-speed PLL clock derived from the crystal. This the CPU clock,
+ * and we assume that it is enabled
+ */
+ regmap_read(map, ASPEED_HPLL_PARAM, &val);
+ aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
+
+ /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
+ regmap_read(map, ASPEED_STRAP, &val);
+ val = (val >> 9) & 0x7;
+ WARN(val == 0, "strapping is zero: cannot determine ahb clock");
+ div = 2 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
+ aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
+
+ /* APB clock clock selection register SCU08 (aka PCLK) */
+ regmap_read(map, ASPEED_CLK_SELECTION, &val);
+ val = (val >> 23) & 0x7;
+ div = 4 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
+ aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
+};
+
+static void __init aspeed_cc_init(struct device_node *np)
+{
+ struct regmap *map;
+ u32 val;
+ int ret;
+ int i;
+
+ scu_base = of_iomap(np, 0);
+ if (!scu_base)
+ return;
+
+ aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
+ sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,
+ GFP_KERNEL);
+ if (!aspeed_clk_data)
+ return;
+
+ /*
+ * This way all clocks fetched before the platform device probes,
+ * except those we assign here for early use, will be deferred.
+ */
+ for (i = 0; i < ASPEED_NUM_CLKS; i++)
+ aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+ map = syscon_node_to_regmap(np);
+ if (IS_ERR(map)) {
+ pr_err("no syscon regmap\n");
+ return;
+ }
+ /*
+ * We check that the regmap works on this very first access,
+ * but as this is an MMIO-backed regmap, subsequent regmap
+ * access is not going to fail and we skip error checks from
+ * this point.
+ */
+ ret = regmap_read(map, ASPEED_STRAP, &val);
+ if (ret) {
+ pr_err("failed to read strapping register\n");
+ return;
+ }
+
+ if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
+ aspeed_ast2400_cc(map);
+ else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
+ aspeed_ast2500_cc(map);
+ else
+ pr_err("unknown platform, failed to add clocks\n");
+
+ aspeed_clk_data->num = ASPEED_NUM_CLKS;
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
+ if (ret)
+ pr_err("failed to add DT provider: %d\n", ret);
+};
+CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
+CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index 5e918e7afaba..48d11f2598e8 100644
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -40,6 +40,10 @@
#define MMCM_REG_FILTER1 0x4e
#define MMCM_REG_FILTER2 0x4f
+#define MMCM_CLKOUT_NOCOUNT BIT(6)
+
+#define MMCM_CLK_DIV_NOCOUNT BIT(12)
+
struct axi_clkgen {
void __iomem *base;
struct clk_hw clk_hw;
@@ -298,13 +302,17 @@ static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned int d, m, dout;
+ unsigned long long tmp;
axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
if (d == 0 || dout == 0 || m == 0)
return -EINVAL;
- return *parent_rate / d * m / dout;
+ tmp = (unsigned long long)*parent_rate * m;
+ tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
+
+ return min_t(unsigned long long, tmp, LONG_MAX);
}
static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
@@ -315,18 +323,33 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
unsigned int reg;
unsigned long long tmp;
- axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
- dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);
+ if (reg & MMCM_CLKOUT_NOCOUNT) {
+ dout = 1;
+ } else {
+ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
+ dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+ }
+
axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);
- d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
- axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
- m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+ if (reg & MMCM_CLK_DIV_NOCOUNT)
+ d = 1;
+ else
+ d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+
+ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);
+ if (reg & MMCM_CLKOUT_NOCOUNT) {
+ m = 1;
+ } else {
+ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
+ m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+ }
if (d == 0 || dout == 0)
return 0;
- tmp = (unsigned long long)(parent_rate / d) * m;
- do_div(tmp, dout);
+ tmp = (unsigned long long)parent_rate * m;
+ tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
return min_t(unsigned long long, tmp, ULONG_MAX);
}
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 4ed516cb7276..b49942b9fe50 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -118,12 +118,11 @@ static unsigned int _get_val(const struct clk_div_table *table,
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
unsigned int val,
const struct clk_div_table *table,
- unsigned long flags)
+ unsigned long flags, unsigned long width)
{
- struct clk_divider *divider = to_clk_divider(hw);
unsigned int div;
- div = _get_div(table, val, flags, divider->width);
+ div = _get_div(table, val, flags, width);
if (!div) {
WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
@@ -145,7 +144,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
val &= div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
- divider->flags);
+ divider->flags, divider->width);
}
static bool _is_valid_table_div(const struct clk_div_table *table,
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753b8709..3a1812f65e5d 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
- struct clockgen_pll_div div[4];
+ struct clockgen_pll_div div[8];
};
#define CLKSEL_VALID 1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
struct clk *clk;
int ret;
+ /*
+ * For platform PLL, there are 8 divider clocks.
+ * For core PLL, there are 4 divider clocks at most.
+ */
+ if (idx != PLATFORM_PLL && i >= 4)
+ break;
+
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
"cg-pll%d-div%d", idx, i + 1);
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 20d90769cced..50e7c341e97e 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -72,7 +72,7 @@ static const char * const si5351_input_names[] = {
"xtal", "clkin"
};
static const char * const si5351_pll_names[] = {
- "plla", "pllb", "vxco"
+ "si5351_plla", "si5351_pllb", "si5351_vxco"
};
static const char * const si5351_msynth_names[] = {
"ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
@@ -903,13 +903,42 @@ static int _si5351_clkout_set_disable_state(
return 0;
}
+static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
+{
+ u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
+
+ switch (val & SI5351_CLK_INPUT_MASK) {
+ case SI5351_CLK_INPUT_XTAL:
+ case SI5351_CLK_INPUT_CLKIN:
+ return; /* pll not used, no need to reset */
+ }
+
+ si5351_reg_write(drvdata, SI5351_PLL_RESET,
+ val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
+ SI5351_PLL_RESET_A);
+
+ dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
+ __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
+ (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
+}
+
static int si5351_clkout_prepare(struct clk_hw *hw)
{
struct si5351_hw_data *hwdata =
container_of(hw, struct si5351_hw_data, hw);
+ struct si5351_platform_data *pdata =
+ hwdata->drvdata->client->dev.platform_data;
si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
SI5351_CLK_POWERDOWN, 0);
+
+ /*
+ * Do a pll soft reset on the parent pll -- needed to get a
+ * deterministic phase relationship between the output clocks.
+ */
+ if (pdata->clkout[hwdata->num].pll_reset)
+ _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
+
si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
(1 << hwdata->num), 0);
return 0;
@@ -1297,6 +1326,9 @@ static int si5351_dt_parse(struct i2c_client *client,
pdata->clkout[num].pll_master =
of_property_read_bool(child, "silabs,pll-master");
+
+ pdata->clkout[num].pll_reset =
+ of_property_read_bool(child, "silabs,pll-reset");
}
client->dev.platform_data = pdata;
@@ -1437,11 +1469,6 @@ static int si5351_i2c_probe(struct i2c_client *client,
}
}
- if (!IS_ERR(drvdata->pxtal))
- clk_prepare_enable(drvdata->pxtal);
- if (!IS_ERR(drvdata->pclkin))
- clk_prepare_enable(drvdata->pclkin);
-
/* register xtal input clock gate */
memset(&init, 0, sizeof(init));
init.name = si5351_input_names[0];
@@ -1456,7 +1483,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
if (ret) {
dev_err(&client->dev, "unable to register %s\n", init.name);
- goto err_clk;
+ return ret;
}
/* register clkin input clock gate */
@@ -1474,7 +1501,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
if (ret) {
dev_err(&client->dev, "unable to register %s\n",
init.name);
- goto err_clk;
+ return ret;
}
}
@@ -1496,7 +1523,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
if (ret) {
dev_err(&client->dev, "unable to register %s\n", init.name);
- goto err_clk;
+ return ret;
}
/* register PLLB or VXCO (Si5351B) */
@@ -1520,7 +1547,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
if (ret) {
dev_err(&client->dev, "unable to register %s\n", init.name);
- goto err_clk;
+ return ret;
}
/* register clk multisync and clk out divider */
@@ -1539,7 +1566,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
ret = -ENOMEM;
- goto err_clk;
+ return ret;
}
for (n = 0; n < num_clocks; n++) {
@@ -1559,7 +1586,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
if (ret) {
dev_err(&client->dev, "unable to register %s\n",
init.name);
- goto err_clk;
+ return ret;
}
}
@@ -1587,7 +1614,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
if (ret) {
dev_err(&client->dev, "unable to register %s\n",
init.name);
- goto err_clk;
+ return ret;
}
/* set initial clkout rate */
@@ -1606,17 +1633,17 @@ static int si5351_i2c_probe(struct i2c_client *client,
drvdata);
if (ret) {
dev_err(&client->dev, "unable to add clk provider\n");
- goto err_clk;
+ return ret;
}
return 0;
+}
-err_clk:
- if (!IS_ERR(drvdata->pxtal))
- clk_disable_unprepare(drvdata->pxtal);
- if (!IS_ERR(drvdata->pclkin))
- clk_disable_unprepare(drvdata->pclkin);
- return ret;
+static int si5351_i2c_remove(struct i2c_client *client)
+{
+ of_clk_del_provider(client->dev.of_node);
+
+ return 0;
}
static const struct i2c_device_id si5351_i2c_ids[] = {
@@ -1634,6 +1661,7 @@ static struct i2c_driver si5351_driver = {
.of_match_table = of_match_ptr(si5351_dt_ids),
},
.probe = si5351_i2c_probe,
+ .remove = si5351_i2c_remove,
.id_table = si5351_i2c_ids,
};
module_i2c_driver(si5351_driver);
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6bc8f0e..da44f8dc1d29 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1424,7 +1424,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
base = of_iomap(np, 0);
if (!base) {
- pr_err("%s: unable to map resource", np->name);
+ pr_err("%s: unable to map resource\n", np->name);
return;
}
diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
index 61c3e40507d3..db2b162c0d4c 100644
--- a/drivers/clk/clk-stm32h7.c
+++ b/drivers/clk/clk-stm32h7.c
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) Gabriel Fernandez 2017
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
- *
- * License terms: GPL V2.0.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (C) STMicroelectronics 2017
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#include <linux/clk.h>
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b56c11f51baf..0f686a9dac3e 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -24,6 +24,7 @@
#include <linux/pm_runtime.h>
#include <linux/sched.h>
#include <linux/clkdev.h>
+#include <linux/stringify.h>
#include "clk.h"
@@ -62,6 +63,7 @@ struct clk_core {
bool orphan;
unsigned int enable_count;
unsigned int prepare_count;
+ unsigned int protect_count;
unsigned long min_rate;
unsigned long max_rate;
unsigned long accuracy;
@@ -86,6 +88,7 @@ struct clk {
const char *con_id;
unsigned long min_rate;
unsigned long max_rate;
+ unsigned int exclusive_count;
struct hlist_node clks_node;
};
@@ -141,10 +144,18 @@ static unsigned long clk_enable_lock(void)
{
unsigned long flags;
- if (!spin_trylock_irqsave(&enable_lock, flags)) {
+ /*
+ * On UP systems, spin_trylock_irqsave() always returns true, even if
+ * we already hold the lock. So, in that case, we rely only on
+ * reference counting.
+ */
+ if (!IS_ENABLED(CONFIG_SMP) ||
+ !spin_trylock_irqsave(&enable_lock, flags)) {
if (enable_owner == current) {
enable_refcnt++;
__acquire(enable_lock);
+ if (!IS_ENABLED(CONFIG_SMP))
+ local_save_flags(flags);
return flags;
}
spin_lock_irqsave(&enable_lock, flags);
@@ -170,6 +181,11 @@ static void clk_enable_unlock(unsigned long flags)
spin_unlock_irqrestore(&enable_lock, flags);
}
+static bool clk_core_rate_is_protected(struct clk_core *core)
+{
+ return core->protect_count;
+}
+
static bool clk_core_is_prepared(struct clk_core *core)
{
bool ret = false;
@@ -382,6 +398,11 @@ bool clk_hw_is_prepared(const struct clk_hw *hw)
return clk_core_is_prepared(hw->core);
}
+bool clk_hw_rate_is_protected(const struct clk_hw *hw)
+{
+ return clk_core_rate_is_protected(hw->core);
+}
+
bool clk_hw_is_enabled(const struct clk_hw *hw)
{
return clk_core_is_enabled(hw->core);
@@ -520,6 +541,139 @@ EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
/*** clk api ***/
+static void clk_core_rate_unprotect(struct clk_core *core)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (WARN_ON(core->protect_count == 0))
+ return;
+
+ if (--core->protect_count > 0)
+ return;
+
+ clk_core_rate_unprotect(core->parent);
+}
+
+static int clk_core_rate_nuke_protect(struct clk_core *core)
+{
+ int ret;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return -EINVAL;
+
+ if (core->protect_count == 0)
+ return 0;
+
+ ret = core->protect_count;
+ core->protect_count = 1;
+ clk_core_rate_unprotect(core);
+
+ return ret;
+}
+
+/**
+ * clk_rate_exclusive_put - release exclusivity over clock rate control
+ * @clk: the clk over which the exclusivity is released
+ *
+ * clk_rate_exclusive_put() completes a critical section during which a clock
+ * consumer cannot tolerate any other consumer making any operation on the
+ * clock which could result in a rate change or rate glitch. Exclusive clocks
+ * cannot have their rate changed, either directly or indirectly due to changes
+ * further up the parent chain of clocks. As a result, clocks up parent chain
+ * also get under exclusive control of the calling consumer.
+ *
+ * If exlusivity is claimed more than once on clock, even by the same consumer,
+ * the rate effectively gets locked as exclusivity can't be preempted.
+ *
+ * Calls to clk_rate_exclusive_put() must be balanced with calls to
+ * clk_rate_exclusive_get(). Calls to this function may sleep, and do not return
+ * error status.
+ */
+void clk_rate_exclusive_put(struct clk *clk)
+{
+ if (!clk)
+ return;
+
+ clk_prepare_lock();
+
+ /*
+ * if there is something wrong with this consumer protect count, stop
+ * here before messing with the provider
+ */
+ if (WARN_ON(clk->exclusive_count <= 0))
+ goto out;
+
+ clk_core_rate_unprotect(clk->core);
+ clk->exclusive_count--;
+out:
+ clk_prepare_unlock();
+}
+EXPORT_SYMBOL_GPL(clk_rate_exclusive_put);
+
+static void clk_core_rate_protect(struct clk_core *core)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (core->protect_count == 0)
+ clk_core_rate_protect(core->parent);
+
+ core->protect_count++;
+}
+
+static void clk_core_rate_restore_protect(struct clk_core *core, int count)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (count == 0)
+ return;
+
+ clk_core_rate_protect(core);
+ core->protect_count = count;
+}
+
+/**
+ * clk_rate_exclusive_get - get exclusivity over the clk rate control
+ * @clk: the clk over which the exclusity of rate control is requested
+ *
+ * clk_rate_exlusive_get() begins a critical section during which a clock
+ * consumer cannot tolerate any other consumer making any operation on the
+ * clock which could result in a rate change or rate glitch. Exclusive clocks
+ * cannot have their rate changed, either directly or indirectly due to changes
+ * further up the parent chain of clocks. As a result, clocks up parent chain
+ * also get under exclusive control of the calling consumer.
+ *
+ * If exlusivity is claimed more than once on clock, even by the same consumer,
+ * the rate effectively gets locked as exclusivity can't be preempted.
+ *
+ * Calls to clk_rate_exclusive_get() should be balanced with calls to
+ * clk_rate_exclusive_put(). Calls to this function may sleep.
+ * Returns 0 on success, -EERROR otherwise
+ */
+int clk_rate_exclusive_get(struct clk *clk)
+{
+ if (!clk)
+ return 0;
+
+ clk_prepare_lock();
+ clk_core_rate_protect(clk->core);
+ clk->exclusive_count++;
+ clk_prepare_unlock();
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(clk_rate_exclusive_get);
+
static void clk_core_unprepare(struct clk_core *core)
{
lockdep_assert_held(&prepare_lock);
@@ -906,10 +1060,9 @@ static int clk_disable_unused(void)
}
late_initcall_sync(clk_disable_unused);
-static int clk_core_round_rate_nolock(struct clk_core *core,
- struct clk_rate_request *req)
+static int clk_core_determine_round_nolock(struct clk_core *core,
+ struct clk_rate_request *req)
{
- struct clk_core *parent;
long rate;
lockdep_assert_held(&prepare_lock);
@@ -917,16 +1070,15 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
if (!core)
return 0;
- parent = core->parent;
- if (parent) {
- req->best_parent_hw = parent->hw;
- req->best_parent_rate = parent->rate;
- } else {
- req->best_parent_hw = NULL;
- req->best_parent_rate = 0;
- }
-
- if (core->ops->determine_rate) {
+ /*
+ * At this point, core protection will be disabled if
+ * - if the provider is not protected at all
+ * - if the calling consumer is the only one which has exclusivity
+ * over the provider
+ */
+ if (clk_core_rate_is_protected(core)) {
+ req->rate = core->rate;
+ } else if (core->ops->determine_rate) {
return core->ops->determine_rate(core->hw, req);
} else if (core->ops->round_rate) {
rate = core->ops->round_rate(core->hw, req->rate,
@@ -935,12 +1087,55 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
return rate;
req->rate = rate;
- } else if (core->flags & CLK_SET_RATE_PARENT) {
- return clk_core_round_rate_nolock(parent, req);
} else {
- req->rate = core->rate;
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void clk_core_init_rate_req(struct clk_core * const core,
+ struct clk_rate_request *req)
+{
+ struct clk_core *parent;
+
+ if (WARN_ON(!core || !req))
+ return;
+
+ parent = core->parent;
+ if (parent) {
+ req->best_parent_hw = parent->hw;
+ req->best_parent_rate = parent->rate;
+ } else {
+ req->best_parent_hw = NULL;
+ req->best_parent_rate = 0;
}
+}
+static bool clk_core_can_round(struct clk_core * const core)
+{
+ if (core->ops->determine_rate || core->ops->round_rate)
+ return true;
+
+ return false;
+}
+
+static int clk_core_round_rate_nolock(struct clk_core *core,
+ struct clk_rate_request *req)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ clk_core_init_rate_req(core, req);
+
+ if (clk_core_can_round(core))
+ return clk_core_determine_round_nolock(core, req);
+ else if (core->flags & CLK_SET_RATE_PARENT)
+ return clk_core_round_rate_nolock(core->parent, req);
+
+ req->rate = core->rate;
return 0;
}
@@ -997,10 +1192,17 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
clk_prepare_lock();
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
req.rate = rate;
ret = clk_core_round_rate_nolock(clk->core, &req);
+
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
if (ret)
@@ -1433,34 +1635,23 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
clk_core_get_boundaries(core, &min_rate, &max_rate);
/* find the closest rate and parent clk/rate */
- if (core->ops->determine_rate) {
+ if (clk_core_can_round(core)) {
struct clk_rate_request req;
req.rate = rate;
req.min_rate = min_rate;
req.max_rate = max_rate;
- if (parent) {
- req.best_parent_hw = parent->hw;
- req.best_parent_rate = parent->rate;
- } else {
- req.best_parent_hw = NULL;
- req.best_parent_rate = 0;
- }
- ret = core->ops->determine_rate(core->hw, &req);
+ clk_core_init_rate_req(core, &req);
+
+ ret = clk_core_determine_round_nolock(core, &req);
if (ret < 0)
return NULL;
best_parent_rate = req.best_parent_rate;
new_rate = req.rate;
parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
- } else if (core->ops->round_rate) {
- ret = core->ops->round_rate(core->hw, rate,
- &best_parent_rate);
- if (ret < 0)
- return NULL;
- new_rate = ret;
if (new_rate < min_rate || new_rate > max_rate)
return NULL;
} else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
@@ -1642,25 +1833,58 @@ static void clk_change_rate(struct clk_core *core)
clk_pm_runtime_put(core);
}
+static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
+ unsigned long req_rate)
+{
+ int ret, cnt;
+ struct clk_rate_request req;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ /* simulate what the rate would be if it could be freely set */
+ cnt = clk_core_rate_nuke_protect(core);
+ if (cnt < 0)
+ return cnt;
+
+ clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
+ req.rate = req_rate;
+
+ ret = clk_core_round_rate_nolock(core, &req);
+
+ /* restore the protection */
+ clk_core_rate_restore_protect(core, cnt);
+
+ return ret ? 0 : req.rate;
+}
+
static int clk_core_set_rate_nolock(struct clk_core *core,
unsigned long req_rate)
{
struct clk_core *top, *fail_clk;
- unsigned long rate = req_rate;
+ unsigned long rate;
int ret = 0;
if (!core)
return 0;
+ rate = clk_core_req_round_rate_nolock(core, req_rate);
+
/* bail early if nothing to do */
if (rate == clk_core_get_rate_nolock(core))
return 0;
+ /* fail on a direct rate set of a protected provider */
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
+
if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
return -EBUSY;
/* calculate new rates and get the topmost changed clock */
- top = clk_calc_new_rates(core, rate);
+ top = clk_calc_new_rates(core, req_rate);
if (!top)
return -EINVAL;
@@ -1719,8 +1943,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
/* prevent racing with updates to the clock topology */
clk_prepare_lock();
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
return ret;
@@ -1728,6 +1958,53 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
EXPORT_SYMBOL_GPL(clk_set_rate);
/**
+ * clk_set_rate_exclusive - specify a new rate get exclusive control
+ * @clk: the clk whose rate is being changed
+ * @rate: the new rate for clk
+ *
+ * This is a combination of clk_set_rate() and clk_rate_exclusive_get()
+ * within a critical section
+ *
+ * This can be used initially to ensure that at least 1 consumer is
+ * statisfied when several consumers are competing for exclusivity over the
+ * same clock provider.
+ *
+ * The exclusivity is not applied if setting the rate failed.
+ *
+ * Calls to clk_rate_exclusive_get() should be balanced with calls to
+ * clk_rate_exclusive_put().
+ *
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
+{
+ int ret;
+
+ if (!clk)
+ return 0;
+
+ /* prevent racing with updates to the clock topology */
+ clk_prepare_lock();
+
+ /*
+ * The temporary protection removal is not here, on purpose
+ * This function is meant to be used instead of clk_rate_protect,
+ * so before the consumer code path protect the clock provider
+ */
+
+ ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (!ret) {
+ clk_core_rate_protect(clk->core);
+ clk->exclusive_count++;
+ }
+
+ clk_prepare_unlock();
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
+
+/**
* clk_set_rate_range - set a rate range for a clock source
* @clk: clock source
* @min: desired minimum clock rate in Hz, inclusive
@@ -1738,6 +2015,7 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
{
int ret = 0;
+ unsigned long old_min, old_max, rate;
if (!clk)
return 0;
@@ -1751,12 +2029,46 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
clk_prepare_lock();
- if (min != clk->min_rate || max != clk->max_rate) {
- clk->min_rate = min;
- clk->max_rate = max;
- ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
+ /* Save the current values in case we need to rollback the change */
+ old_min = clk->min_rate;
+ old_max = clk->max_rate;
+ clk->min_rate = min;
+ clk->max_rate = max;
+
+ rate = clk_core_get_rate_nolock(clk->core);
+ if (rate < min || rate > max) {
+ /*
+ * FIXME:
+ * We are in bit of trouble here, current rate is outside the
+ * the requested range. We are going try to request appropriate
+ * range boundary but there is a catch. It may fail for the
+ * usual reason (clock broken, clock protected, etc) but also
+ * because:
+ * - round_rate() was not favorable and fell on the wrong
+ * side of the boundary
+ * - the determine_rate() callback does not really check for
+ * this corner case when determining the rate
+ */
+
+ if (rate < min)
+ rate = min;
+ else
+ rate = max;
+
+ ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (ret) {
+ /* rollback the changes */
+ clk->min_rate = old_min;
+ clk->max_rate = old_max;
+ }
}
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
return ret;
@@ -1877,32 +2189,31 @@ bool clk_has_parent(struct clk *clk, struct clk *parent)
}
EXPORT_SYMBOL_GPL(clk_has_parent);
-static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
+static int clk_core_set_parent_nolock(struct clk_core *core,
+ struct clk_core *parent)
{
int ret = 0;
int p_index = 0;
unsigned long p_rate = 0;
+ lockdep_assert_held(&prepare_lock);
+
if (!core)
return 0;
- /* prevent racing with updates to the clock topology */
- clk_prepare_lock();
-
if (core->parent == parent)
- goto out;
+ return 0;
/* verify ops for for multi-parent clks */
- if ((core->num_parents > 1) && (!core->ops->set_parent)) {
- ret = -ENOSYS;
- goto out;
- }
+ if (core->num_parents > 1 && !core->ops->set_parent)
+ return -EPERM;
/* check that we are allowed to re-parent if the clock is in use */
- if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
- ret = -EBUSY;
- goto out;
- }
+ if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count)
+ return -EBUSY;
+
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
/* try finding the new parent index */
if (parent) {
@@ -1910,15 +2221,14 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
if (p_index < 0) {
pr_debug("%s: clk %s can not be parent of clk %s\n",
__func__, parent->name, core->name);
- ret = p_index;
- goto out;
+ return p_index;
}
p_rate = parent->rate;
}
ret = clk_pm_runtime_get(core);
if (ret)
- goto out;
+ return ret;
/* propagate PRE_RATE_CHANGE notifications */
ret = __clk_speculate_rates(core, p_rate);
@@ -1940,8 +2250,6 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
runtime_put:
clk_pm_runtime_put(core);
-out:
- clk_prepare_unlock();
return ret;
}
@@ -1965,13 +2273,50 @@ out:
*/
int clk_set_parent(struct clk *clk, struct clk *parent)
{
+ int ret;
+
if (!clk)
return 0;
- return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
+ clk_prepare_lock();
+
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
+ ret = clk_core_set_parent_nolock(clk->core,
+ parent ? parent->core : NULL);
+
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
+ clk_prepare_unlock();
+
+ return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
+static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
+{
+ int ret = -EINVAL;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
+
+ trace_clk_set_phase(core, degrees);
+
+ if (core->ops->set_phase)
+ ret = core->ops->set_phase(core->hw, degrees);
+
+ trace_clk_set_phase_complete(core, degrees);
+
+ return ret;
+}
+
/**
* clk_set_phase - adjust the phase shift of a clock signal
* @clk: clock signal source
@@ -1994,7 +2339,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
*/
int clk_set_phase(struct clk *clk, int degrees)
{
- int ret = -EINVAL;
+ int ret;
if (!clk)
return 0;
@@ -2006,15 +2351,13 @@ int clk_set_phase(struct clk *clk, int degrees)
clk_prepare_lock();
- trace_clk_set_phase(clk->core, degrees);
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
- if (clk->core->ops->set_phase)
- ret = clk->core->ops->set_phase(clk->core->hw, degrees);
+ ret = clk_core_set_phase_nolock(clk->core, degrees);
- trace_clk_set_phase_complete(clk->core, degrees);
-
- if (!ret)
- clk->core->phase = degrees;
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
clk_prepare_unlock();
@@ -2102,11 +2445,12 @@ static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
if (!c)
return;
- seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
+ seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %-3d\n",
level * 3 + 1, "",
30 - level * 3, c->name,
- c->enable_count, c->prepare_count, clk_core_get_rate(c),
- clk_core_get_accuracy(c), clk_core_get_phase(c));
+ c->enable_count, c->prepare_count, c->protect_count,
+ clk_core_get_rate(c), clk_core_get_accuracy(c),
+ clk_core_get_phase(c));
}
static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
@@ -2128,7 +2472,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
struct clk_core *c;
struct hlist_head **lists = (struct hlist_head **)s->private;
- seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
+ seq_puts(s, " enable prepare protect \n");
+ seq_puts(s, " clock count count count rate accuracy phase\n");
seq_puts(s, "----------------------------------------------------------------------------------------\n");
clk_prepare_lock();
@@ -2164,6 +2509,7 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
seq_printf(s, "\"%s\": { ", c->name);
seq_printf(s, "\"enable_count\": %d,", c->enable_count);
seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
+ seq_printf(s, "\"protect_count\": %d,", c->protect_count);
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
@@ -2223,6 +2569,58 @@ static const struct file_operations clk_dump_fops = {
.release = single_release,
};
+static const struct {
+ unsigned long flag;
+ const char *name;
+} clk_flags[] = {
+#define ENTRY(f) { f, __stringify(f) }
+ ENTRY(CLK_SET_RATE_GATE),
+ ENTRY(CLK_SET_PARENT_GATE),
+ ENTRY(CLK_SET_RATE_PARENT),
+ ENTRY(CLK_IGNORE_UNUSED),
+ ENTRY(CLK_IS_BASIC),
+ ENTRY(CLK_GET_RATE_NOCACHE),
+ ENTRY(CLK_SET_RATE_NO_REPARENT),
+ ENTRY(CLK_GET_ACCURACY_NOCACHE),
+ ENTRY(CLK_RECALC_NEW_RATES),
+ ENTRY(CLK_SET_RATE_UNGATE),
+ ENTRY(CLK_IS_CRITICAL),
+ ENTRY(CLK_OPS_PARENT_ENABLE),
+#undef ENTRY
+};
+
+static int clk_flags_dump(struct seq_file *s, void *data)
+{
+ struct clk_core *core = s->private;
+ unsigned long flags = core->flags;
+ unsigned int i;
+
+ for (i = 0; flags && i < ARRAY_SIZE(clk_flags); i++) {
+ if (flags & clk_flags[i].flag) {
+ seq_printf(s, "%s\n", clk_flags[i].name);
+ flags &= ~clk_flags[i].flag;
+ }
+ }
+ if (flags) {
+ /* Unknown flags */
+ seq_printf(s, "0x%lx\n", flags);
+ }
+
+ return 0;
+}
+
+static int clk_flags_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clk_flags_dump, inode->i_private);
+}
+
+static const struct file_operations clk_flags_fops = {
+ .open = clk_flags_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int possible_parents_dump(struct seq_file *s, void *data)
{
struct clk_core *core = s->private;
@@ -2264,43 +2662,46 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
core->dentry = d;
- d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
- (u32 *)&core->rate);
+ d = debugfs_create_ulong("clk_rate", 0444, core->dentry, &core->rate);
if (!d)
goto err_out;
- d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
- (u32 *)&core->accuracy);
+ d = debugfs_create_ulong("clk_accuracy", 0444, core->dentry,
+ &core->accuracy);
if (!d)
goto err_out;
- d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
- (u32 *)&core->phase);
+ d = debugfs_create_u32("clk_phase", 0444, core->dentry, &core->phase);
if (!d)
goto err_out;
- d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
- (u32 *)&core->flags);
+ d = debugfs_create_file("clk_flags", 0444, core->dentry, core,
+ &clk_flags_fops);
if (!d)
goto err_out;
- d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
- (u32 *)&core->prepare_count);
+ d = debugfs_create_u32("clk_prepare_count", 0444, core->dentry,
+ &core->prepare_count);
if (!d)
goto err_out;
- d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
- (u32 *)&core->enable_count);
+ d = debugfs_create_u32("clk_enable_count", 0444, core->dentry,
+ &core->enable_count);
if (!d)
goto err_out;
- d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
- (u32 *)&core->notifier_count);
+ d = debugfs_create_u32("clk_protect_count", 0444, core->dentry,
+ &core->protect_count);
+ if (!d)
+ goto err_out;
+
+ d = debugfs_create_u32("clk_notifier_count", 0444, core->dentry,
+ &core->notifier_count);
if (!d)
goto err_out;
if (core->num_parents > 1) {
- d = debugfs_create_file("clk_possible_parents", S_IRUGO,
+ d = debugfs_create_file("clk_possible_parents", 0444,
core->dentry, core, &possible_parents_fops);
if (!d)
goto err_out;
@@ -2336,12 +2737,8 @@ static int clk_debug_register(struct clk_core *core)
mutex_lock(&clk_debug_lock);
hlist_add_head(&core->debug_node, &clk_debug_list);
-
- if (!inited)
- goto unlock;
-
- ret = clk_debug_create_one(core, rootdir);
-unlock:
+ if (inited)
+ ret = clk_debug_create_one(core, rootdir);
mutex_unlock(&clk_debug_lock);
return ret;
@@ -2396,22 +2793,22 @@ static int __init clk_debug_init(void)
if (!rootdir)
return -ENOMEM;
- d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
+ d = debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
&clk_summary_fops);
if (!d)
return -ENOMEM;
- d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
+ d = debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
&clk_dump_fops);
if (!d)
return -ENOMEM;
- d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
+ d = debugfs_create_file("clk_orphan_summary", 0444, rootdir,
&orphan_list, &clk_summary_fops);
if (!d)
return -ENOMEM;
- d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
+ d = debugfs_create_file("clk_orphan_dump", 0444, rootdir,
&orphan_list, &clk_dump_fops);
if (!d)
return -ENOMEM;
@@ -2576,14 +2973,17 @@ static int __clk_core_init(struct clk_core *core)
*/
hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
struct clk_core *parent = __clk_init_parent(orphan);
+ unsigned long flags;
/*
* we could call __clk_set_parent, but that would result in a
* redundant call to the .set_rate op, if it exists
*/
if (parent) {
- __clk_set_parent_before(orphan, parent);
- __clk_set_parent_after(orphan, parent, NULL);
+ /* update the clk tree topology */
+ flags = clk_enable_lock();
+ clk_reparent(orphan, parent);
+ clk_enable_unlock(flags);
__clk_recalc_accuracies(orphan);
__clk_recalc_rates(orphan, 0);
}
@@ -2684,7 +3084,13 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
ret = -ENOMEM;
goto fail_name;
}
+
+ if (WARN_ON(!hw->init->ops)) {
+ ret = -EINVAL;
+ goto fail_ops;
+ }
core->ops = hw->init->ops;
+
if (dev && pm_runtime_enabled(dev))
core->dev = dev;
if (dev && dev->driver)
@@ -2746,6 +3152,7 @@ fail_parent_names_copy:
kfree_const(core->parent_names[i]);
kfree(core->parent_names);
fail_parent_names:
+fail_ops:
kfree_const(core->name);
fail_name:
kfree(core);
@@ -2857,7 +3264,7 @@ void clk_unregister(struct clk *clk)
/* Reparent all children to the orphan list. */
hlist_for_each_entry_safe(child, t, &clk->core->children,
child_node)
- clk_core_set_parent(child, NULL);
+ clk_core_set_parent_nolock(child, NULL);
}
hlist_del_init(&clk->core->child_node);
@@ -2865,6 +3272,11 @@ void clk_unregister(struct clk *clk)
if (clk->core->prepare_count)
pr_warn("%s: unregistering prepared clock: %s\n",
__func__, clk->core->name);
+
+ if (clk->core->protect_count)
+ pr_warn("%s: unregistering protected clock: %s\n",
+ __func__, clk->core->name);
+
kref_put(&clk->core->ref, __clk_release);
unlock:
clk_prepare_unlock();
@@ -3023,6 +3435,18 @@ void __clk_put(struct clk *clk)
clk_prepare_lock();
+ /*
+ * Before calling clk_put, all calls to clk_rate_exclusive_get() from a
+ * given user should be balanced with calls to clk_rate_exclusive_put()
+ * and by that same consumer
+ */
+ if (WARN_ON(clk->exclusive_count)) {
+ /* We voiced our concern, let's sanitize the situation */
+ clk->core->protect_count -= (clk->exclusive_count - 1);
+ clk_core_rate_unprotect(clk->core);
+ clk->exclusive_count = 0;
+ }
+
hlist_del(&clk->clks_node);
if (clk->min_rate > clk->core->req_rate ||
clk->max_rate < clk->core->req_rate)
@@ -3559,7 +3983,7 @@ static int parent_ready(struct device_node *np)
* of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
* @np: Device node pointer associated with clock provider
* @index: clock index
- * @flags: pointer to clk_core->flags
+ * @flags: pointer to top-level framework flags
*
* Detects if the clock-critical property exists and, if so, sets the
* corresponding CLK_IS_CRITICAL flag.
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
index 00b35a13cdf3..70c0ba6336c1 100644
--- a/drivers/clk/clk.h
+++ b/drivers/clk/clk.h
@@ -20,6 +20,8 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
const char *con_id);
void __clk_free_clk(struct clk *clk);
+int __clk_get(struct clk *clk);
+void __clk_put(struct clk *clk);
#else
/* All these casts to avoid ifdefs in clkdev... */
static inline struct clk *
@@ -32,5 +34,7 @@ static struct clk_hw *__clk_get_hw(struct clk *clk)
{
return (struct clk_hw *)clk;
}
+static inline int __clk_get(struct clk *clk) { return 1; }
+static inline void __clk_put(struct clk *clk) { }
#endif
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6b2f29df3f70..7513411140b6 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -256,7 +256,7 @@ vclkdev_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
{
struct clk_lookup_alloc *cla;
- cla = __clkdev_alloc(sizeof(*cla));
+ cla = kzalloc(sizeof(*cla), GFP_KERNEL);
if (!cla)
return NULL;
diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c
index 4ae624425e9d..d413ade95c99 100644
--- a/drivers/clk/h8300/clk-div.c
+++ b/drivers/clk/h8300/clk-div.c
@@ -24,13 +24,13 @@ static void __init h8300_div_clk_setup(struct device_node *node)
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
- pr_err("%s: no parent found", clk_name);
+ pr_err("%s: no parent found\n", clk_name);
return;
}
divcr = of_iomap(node, 0);
if (divcr == NULL) {
- pr_err("%s: failed to map divide register", clk_name);
+ pr_err("%s: failed to map divide register\n", clk_name);
goto error;
}
offset = (unsigned long)divcr & 3;
diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c
index fc24b0b55a3d..b68045d8b921 100644
--- a/drivers/clk/h8300/clk-h8s2678.c
+++ b/drivers/clk/h8300/clk-h8s2678.c
@@ -93,7 +93,7 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
- pr_err("%s: no parent found", clk_name);
+ pr_err("%s: no parent found\n", clk_name);
return;
}
@@ -104,13 +104,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
pll_clock->sckcr = of_iomap(node, 0);
if (pll_clock->sckcr == NULL) {
- pr_err("%s: failed to map divide register", clk_name);
+ pr_err("%s: failed to map divide register\n", clk_name);
goto free_clock;
}
pll_clock->pllcr = of_iomap(node, 1);
if (pll_clock->pllcr == NULL) {
- pr_err("%s: failed to map multiply register", clk_name);
+ pr_err("%s: failed to map multiply register\n", clk_name);
goto unmap_sckcr;
}
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 7098bfd32b1b..1bd43550e4c8 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -49,3 +49,9 @@ config STUB_CLK_HI6220
default ARCH_HISI
help
Build the Hisilicon Hi6220 stub clock driver.
+
+config STUB_CLK_HI3660
+ bool "Hi3660 Stub Clock Driver"
+ depends on COMMON_CLK_HI3660 && MAILBOX
+ help
+ Build the Hisilicon Hi3660 stub clock driver.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 0e55612112af..4806fc2cb4ac 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
+obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o
diff --git a/drivers/clk/hisilicon/clk-hi3660-stub.c b/drivers/clk/hisilicon/clk-hi3660-stub.c
new file mode 100644
index 000000000000..9b6c72bbddf9
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3660-stub.c
@@ -0,0 +1,185 @@
+/*
+ * Hisilicon clock driver
+ *
+ * Copyright (c) 2013-2017 Hisilicon Limited.
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * Author: Kai Zhao <zhaokai1@hisilicon.com>
+ * Tao Wang <kevin.wangtao@hisilicon.com>
+ * Leo Yan <leo.yan@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/hi3660-clock.h>
+
+#define HI3660_STUB_CLOCK_DATA (0x70)
+#define MHZ (1000 * 1000)
+
+#define DEFINE_CLK_STUB(_id, _cmd, _name) \
+ { \
+ .id = (_id), \
+ .cmd = (_cmd), \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &hi3660_stub_clk_ops, \
+ .num_parents = 0, \
+ .flags = CLK_GET_RATE_NOCACHE, \
+ }, \
+ },
+
+#define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw)
+
+struct hi3660_stub_clk_chan {
+ struct mbox_client cl;
+ struct mbox_chan *mbox;
+};
+
+struct hi3660_stub_clk {
+ unsigned int id;
+ struct clk_hw hw;
+ unsigned int cmd;
+ unsigned int msg[8];
+ unsigned int rate;
+};
+
+static void __iomem *freq_reg;
+static struct hi3660_stub_clk_chan stub_clk_chan;
+
+static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ /*
+ * LPM3 writes back the CPU frequency in shared SRAM so read
+ * back the frequency.
+ */
+ stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ;
+ return stub_clk->rate;
+}
+
+static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ /*
+ * LPM3 handles rate rounding so just return whatever
+ * rate is requested.
+ */
+ return rate;
+}
+
+static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ stub_clk->msg[0] = stub_clk->cmd;
+ stub_clk->msg[1] = rate / MHZ;
+
+ dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n",
+ stub_clk->msg[0], stub_clk->msg[1]);
+
+ mbox_send_message(stub_clk_chan.mbox, stub_clk->msg);
+ mbox_client_txdone(stub_clk_chan.mbox, 0);
+
+ stub_clk->rate = rate;
+ return 0;
+}
+
+static const struct clk_ops hi3660_stub_clk_ops = {
+ .recalc_rate = hi3660_stub_clk_recalc_rate,
+ .round_rate = hi3660_stub_clk_round_rate,
+ .set_rate = hi3660_stub_clk_set_rate,
+};
+
+static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = {
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
+};
+
+static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= HI3660_CLK_STUB_NUM) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &hi3660_stub_clks[idx].hw;
+}
+
+static int hi3660_stub_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ unsigned int i;
+ int ret;
+
+ /* Use mailbox client without blocking */
+ stub_clk_chan.cl.dev = dev;
+ stub_clk_chan.cl.tx_done = NULL;
+ stub_clk_chan.cl.tx_block = false;
+ stub_clk_chan.cl.knows_txdone = false;
+
+ /* Allocate mailbox channel */
+ stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
+ if (IS_ERR(stub_clk_chan.mbox))
+ return PTR_ERR(stub_clk_chan.mbox);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ freq_reg = devm_ioremap(dev, res->start, resource_size(res));
+ if (!freq_reg)
+ return -ENOMEM;
+
+ freq_reg += HI3660_STUB_CLOCK_DATA;
+
+ for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
+ ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, hi3660_stub_clk_hw_get,
+ hi3660_stub_clks);
+}
+
+static const struct of_device_id hi3660_stub_clk_of_match[] = {
+ { .compatible = "hisilicon,hi3660-stub-clk", },
+ {}
+};
+
+static struct platform_driver hi3660_stub_clk_driver = {
+ .probe = hi3660_stub_clk_probe,
+ .driver = {
+ .name = "hi3660-stub-clk",
+ .of_match_table = hi3660_stub_clk_of_match,
+ },
+};
+
+static int __init hi3660_stub_clk_init(void)
+{
+ return platform_driver_register(&hi3660_stub_clk_driver);
+}
+subsys_initcall(hi3660_stub_clk_init);
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
index a1c1f684ad58..9f46cf9dcc65 100644
--- a/drivers/clk/hisilicon/clkdivider-hi6220.c
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -56,7 +56,7 @@ static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw,
val &= div_mask(dclk->width);
return divider_recalc_rate(hw, parent_rate, val, dclk->table,
- CLK_DIVIDER_ROUND_CLOSEST);
+ CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
}
static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c
index 7bcaf270db11..c864992e6983 100644
--- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -257,10 +257,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
- clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
- clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
- clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
- clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
@@ -361,6 +357,10 @@ static void __init mx50_clocks_init(struct device_node *np)
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+ clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+ clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+ clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+ clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -562,6 +562,10 @@ static void __init mx53_clocks_init(struct device_node *np)
clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
+ clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+ clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+ clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+ clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 59dc0aad553c..1f9ea0f21df1 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1,136 +1,140 @@
#
-# MediaTek SoC drivers
+# MediaTek Clock Drivers
#
+menu "Clock driver for MediaTek SoC"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+
config COMMON_CLK_MEDIATEK
bool
+ select RESET_CONTROLLER
---help---
- Mediatek SoCs' clock support.
+ MediaTek SoCs' clock support.
config COMMON_CLK_MT2701
- bool "Clock driver for Mediatek MT2701"
+ bool "Clock driver for MediaTek MT2701"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM
---help---
- This driver supports Mediatek MT2701 basic clocks.
+ This driver supports MediaTek MT2701 basic clocks.
config COMMON_CLK_MT2701_MMSYS
- bool "Clock driver for Mediatek MT2701 mmsys"
+ bool "Clock driver for MediaTek MT2701 mmsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 mmsys clocks.
+ This driver supports MediaTek MT2701 mmsys clocks.
config COMMON_CLK_MT2701_IMGSYS
- bool "Clock driver for Mediatek MT2701 imgsys"
+ bool "Clock driver for MediaTek MT2701 imgsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 imgsys clocks.
+ This driver supports MediaTek MT2701 imgsys clocks.
config COMMON_CLK_MT2701_VDECSYS
- bool "Clock driver for Mediatek MT2701 vdecsys"
+ bool "Clock driver for MediaTek MT2701 vdecsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 vdecsys clocks.
+ This driver supports MediaTek MT2701 vdecsys clocks.
config COMMON_CLK_MT2701_HIFSYS
- bool "Clock driver for Mediatek MT2701 hifsys"
+ bool "Clock driver for MediaTek MT2701 hifsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 hifsys clocks.
+ This driver supports MediaTek MT2701 hifsys clocks.
config COMMON_CLK_MT2701_ETHSYS
- bool "Clock driver for Mediatek MT2701 ethsys"
+ bool "Clock driver for MediaTek MT2701 ethsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 ethsys clocks.
+ This driver supports MediaTek MT2701 ethsys clocks.
config COMMON_CLK_MT2701_BDPSYS
- bool "Clock driver for Mediatek MT2701 bdpsys"
+ bool "Clock driver for MediaTek MT2701 bdpsys"
depends on COMMON_CLK_MT2701
---help---
- This driver supports Mediatek MT2701 bdpsys clocks.
+ This driver supports MediaTek MT2701 bdpsys clocks.
config COMMON_CLK_MT2712
- bool "Clock driver for Mediatek MT2712"
+ bool "Clock driver for MediaTek MT2712"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM64
---help---
- This driver supports Mediatek MT2712 basic clocks.
+ This driver supports MediaTek MT2712 basic clocks.
config COMMON_CLK_MT2712_BDPSYS
- bool "Clock driver for Mediatek MT2712 bdpsys"
+ bool "Clock driver for MediaTek MT2712 bdpsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 bdpsys clocks.
+ This driver supports MediaTek MT2712 bdpsys clocks.
config COMMON_CLK_MT2712_IMGSYS
- bool "Clock driver for Mediatek MT2712 imgsys"
+ bool "Clock driver for MediaTek MT2712 imgsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 imgsys clocks.
+ This driver supports MediaTek MT2712 imgsys clocks.
config COMMON_CLK_MT2712_JPGDECSYS
- bool "Clock driver for Mediatek MT2712 jpgdecsys"
+ bool "Clock driver for MediaTek MT2712 jpgdecsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 jpgdecsys clocks.
+ This driver supports MediaTek MT2712 jpgdecsys clocks.
config COMMON_CLK_MT2712_MFGCFG
- bool "Clock driver for Mediatek MT2712 mfgcfg"
+ bool "Clock driver for MediaTek MT2712 mfgcfg"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 mfgcfg clocks.
+ This driver supports MediaTek MT2712 mfgcfg clocks.
config COMMON_CLK_MT2712_MMSYS
- bool "Clock driver for Mediatek MT2712 mmsys"
+ bool "Clock driver for MediaTek MT2712 mmsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 mmsys clocks.
+ This driver supports MediaTek MT2712 mmsys clocks.
config COMMON_CLK_MT2712_VDECSYS
- bool "Clock driver for Mediatek MT2712 vdecsys"
+ bool "Clock driver for MediaTek MT2712 vdecsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 vdecsys clocks.
+ This driver supports MediaTek MT2712 vdecsys clocks.
config COMMON_CLK_MT2712_VENCSYS
- bool "Clock driver for Mediatek MT2712 vencsys"
+ bool "Clock driver for MediaTek MT2712 vencsys"
depends on COMMON_CLK_MT2712
---help---
- This driver supports Mediatek MT2712 vencsys clocks.
+ This driver supports MediaTek MT2712 vencsys clocks.
config COMMON_CLK_MT6797
- bool "Clock driver for Mediatek MT6797"
+ bool "Clock driver for MediaTek MT6797"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM64
---help---
- This driver supports Mediatek MT6797 basic clocks.
+ This driver supports MediaTek MT6797 basic clocks.
config COMMON_CLK_MT6797_MMSYS
- bool "Clock driver for Mediatek MT6797 mmsys"
+ bool "Clock driver for MediaTek MT6797 mmsys"
depends on COMMON_CLK_MT6797
---help---
- This driver supports Mediatek MT6797 mmsys clocks.
+ This driver supports MediaTek MT6797 mmsys clocks.
config COMMON_CLK_MT6797_IMGSYS
- bool "Clock driver for Mediatek MT6797 imgsys"
+ bool "Clock driver for MediaTek MT6797 imgsys"
depends on COMMON_CLK_MT6797
---help---
- This driver supports Mediatek MT6797 imgsys clocks.
+ This driver supports MediaTek MT6797 imgsys clocks.
config COMMON_CLK_MT6797_VDECSYS
- bool "Clock driver for Mediatek MT6797 vdecsys"
+ bool "Clock driver for MediaTek MT6797 vdecsys"
depends on COMMON_CLK_MT6797
---help---
- This driver supports Mediatek MT6797 vdecsys clocks.
+ This driver supports MediaTek MT6797 vdecsys clocks.
config COMMON_CLK_MT6797_VENCSYS
- bool "Clock driver for Mediatek MT6797 vencsys"
+ bool "Clock driver for MediaTek MT6797 vencsys"
depends on COMMON_CLK_MT6797
---help---
- This driver supports Mediatek MT6797 vencsys clocks.
+ This driver supports MediaTek MT6797 vencsys clocks.
config COMMON_CLK_MT7622
bool "Clock driver for MediaTek MT7622"
@@ -163,17 +167,18 @@ config COMMON_CLK_MT7622_AUDSYS
to audio consumers such as I2S and TDM.
config COMMON_CLK_MT8135
- bool "Clock driver for Mediatek MT8135"
+ bool "Clock driver for MediaTek MT8135"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM
---help---
- This driver supports Mediatek MT8135 clocks.
+ This driver supports MediaTek MT8135 clocks.
config COMMON_CLK_MT8173
- bool "Clock driver for Mediatek MT8173"
+ bool "Clock driver for MediaTek MT8173"
depends on ARCH_MEDIATEK || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK
---help---
- This driver supports Mediatek MT8173 clocks.
+ This driver supports MediaTek MT8173 clocks.
+endmenu
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index c421ffcd49ff..5160fdc4bbb8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
-obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f10250dcece4..f83c2bbb677e 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -20,6 +20,7 @@
#include <linux/clk-provider.h>
struct clk;
+struct clk_onecell_data;
#define MAX_MUX_GATE_BIT 31
#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
@@ -228,14 +229,7 @@ void mtk_clk_register_plls(struct device_node *node,
struct clk *mtk_clk_register_ref2usb_tx(const char *name,
const char *parent_name, void __iomem *reg);
-#ifdef CONFIG_RESET_CONTROLLER
void mtk_register_reset_controller(struct device_node *np,
unsigned int num_regs, int regofs);
-#else
-static inline void mtk_register_reset_controller(struct device_node *np,
- unsigned int num_regs, int regofs)
-{
-}
-#endif
#endif /* __DRV_CLK_MTK_H */
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d2d0174a6eca..7694302c70a4 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
help
Support for the clock controller on AmLogic S905 devices, aka gxbb.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_AXG
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ help
+ Support for the clock controller on AmLogic A113D devices, aka axg.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index b139d41b25da..3c03ce583798 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
new file mode 100644
index 000000000000..1294f3ad7cd5
--- /dev/null
+++ b/drivers/clk/meson/axg.c
@@ -0,0 +1,938 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+#include "clkc.h"
+#include "axg.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static const struct pll_rate_table sys_pll_rate_table[] = {
+ PLL_RATE(24000000, 56, 1, 2),
+ PLL_RATE(48000000, 64, 1, 2),
+ PLL_RATE(72000000, 72, 1, 2),
+ PLL_RATE(96000000, 64, 1, 2),
+ PLL_RATE(120000000, 80, 1, 2),
+ PLL_RATE(144000000, 96, 1, 2),
+ PLL_RATE(168000000, 56, 1, 1),
+ PLL_RATE(192000000, 64, 1, 1),
+ PLL_RATE(216000000, 72, 1, 1),
+ PLL_RATE(240000000, 80, 1, 1),
+ PLL_RATE(264000000, 88, 1, 1),
+ PLL_RATE(288000000, 96, 1, 1),
+ PLL_RATE(312000000, 52, 1, 2),
+ PLL_RATE(336000000, 56, 1, 2),
+ PLL_RATE(360000000, 60, 1, 2),
+ PLL_RATE(384000000, 64, 1, 2),
+ PLL_RATE(408000000, 68, 1, 2),
+ PLL_RATE(432000000, 72, 1, 2),
+ PLL_RATE(456000000, 76, 1, 2),
+ PLL_RATE(480000000, 80, 1, 2),
+ PLL_RATE(504000000, 84, 1, 2),
+ PLL_RATE(528000000, 88, 1, 2),
+ PLL_RATE(552000000, 92, 1, 2),
+ PLL_RATE(576000000, 96, 1, 2),
+ PLL_RATE(600000000, 50, 1, 1),
+ PLL_RATE(624000000, 52, 1, 1),
+ PLL_RATE(648000000, 54, 1, 1),
+ PLL_RATE(672000000, 56, 1, 1),
+ PLL_RATE(696000000, 58, 1, 1),
+ PLL_RATE(720000000, 60, 1, 1),
+ PLL_RATE(744000000, 62, 1, 1),
+ PLL_RATE(768000000, 64, 1, 1),
+ PLL_RATE(792000000, 66, 1, 1),
+ PLL_RATE(816000000, 68, 1, 1),
+ PLL_RATE(840000000, 70, 1, 1),
+ PLL_RATE(864000000, 72, 1, 1),
+ PLL_RATE(888000000, 74, 1, 1),
+ PLL_RATE(912000000, 76, 1, 1),
+ PLL_RATE(936000000, 78, 1, 1),
+ PLL_RATE(960000000, 80, 1, 1),
+ PLL_RATE(984000000, 82, 1, 1),
+ PLL_RATE(1008000000, 84, 1, 1),
+ PLL_RATE(1032000000, 86, 1, 1),
+ PLL_RATE(1056000000, 88, 1, 1),
+ PLL_RATE(1080000000, 90, 1, 1),
+ PLL_RATE(1104000000, 92, 1, 1),
+ PLL_RATE(1128000000, 94, 1, 1),
+ PLL_RATE(1152000000, 96, 1, 1),
+ PLL_RATE(1176000000, 98, 1, 1),
+ PLL_RATE(1200000000, 50, 1, 0),
+ PLL_RATE(1224000000, 51, 1, 0),
+ PLL_RATE(1248000000, 52, 1, 0),
+ PLL_RATE(1272000000, 53, 1, 0),
+ PLL_RATE(1296000000, 54, 1, 0),
+ PLL_RATE(1320000000, 55, 1, 0),
+ PLL_RATE(1344000000, 56, 1, 0),
+ PLL_RATE(1368000000, 57, 1, 0),
+ PLL_RATE(1392000000, 58, 1, 0),
+ PLL_RATE(1416000000, 59, 1, 0),
+ PLL_RATE(1440000000, 60, 1, 0),
+ PLL_RATE(1464000000, 61, 1, 0),
+ PLL_RATE(1488000000, 62, 1, 0),
+ PLL_RATE(1512000000, 63, 1, 0),
+ PLL_RATE(1536000000, 64, 1, 0),
+ PLL_RATE(1560000000, 65, 1, 0),
+ PLL_RATE(1584000000, 66, 1, 0),
+ PLL_RATE(1608000000, 67, 1, 0),
+ PLL_RATE(1632000000, 68, 1, 0),
+ PLL_RATE(1656000000, 68, 1, 0),
+ PLL_RATE(1680000000, 68, 1, 0),
+ PLL_RATE(1704000000, 68, 1, 0),
+ PLL_RATE(1728000000, 69, 1, 0),
+ PLL_RATE(1752000000, 69, 1, 0),
+ PLL_RATE(1776000000, 69, 1, 0),
+ PLL_RATE(1800000000, 69, 1, 0),
+ PLL_RATE(1824000000, 70, 1, 0),
+ PLL_RATE(1848000000, 70, 1, 0),
+ PLL_RATE(1872000000, 70, 1, 0),
+ PLL_RATE(1896000000, 70, 1, 0),
+ PLL_RATE(1920000000, 71, 1, 0),
+ PLL_RATE(1944000000, 71, 1, 0),
+ PLL_RATE(1968000000, 71, 1, 0),
+ PLL_RATE(1992000000, 71, 1, 0),
+ PLL_RATE(2016000000, 72, 1, 0),
+ PLL_RATE(2040000000, 72, 1, 0),
+ PLL_RATE(2064000000, 72, 1, 0),
+ PLL_RATE(2088000000, 72, 1, 0),
+ PLL_RATE(2112000000, 73, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct meson_clk_pll axg_fixed_pll = {
+ .m = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_pll axg_sys_pll = {
+ .m = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 10,
+ .width = 2,
+ },
+ .rate_table = sys_pll_rate_table,
+ .rate_count = ARRAY_SIZE(sys_pll_rate_table),
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_pll",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
+ PLL_RATE(240000000, 40, 1, 2),
+ PLL_RATE(246000000, 41, 1, 2),
+ PLL_RATE(252000000, 42, 1, 2),
+ PLL_RATE(258000000, 43, 1, 2),
+ PLL_RATE(264000000, 44, 1, 2),
+ PLL_RATE(270000000, 45, 1, 2),
+ PLL_RATE(276000000, 46, 1, 2),
+ PLL_RATE(282000000, 47, 1, 2),
+ PLL_RATE(288000000, 48, 1, 2),
+ PLL_RATE(294000000, 49, 1, 2),
+ PLL_RATE(300000000, 50, 1, 2),
+ PLL_RATE(306000000, 51, 1, 2),
+ PLL_RATE(312000000, 52, 1, 2),
+ PLL_RATE(318000000, 53, 1, 2),
+ PLL_RATE(324000000, 54, 1, 2),
+ PLL_RATE(330000000, 55, 1, 2),
+ PLL_RATE(336000000, 56, 1, 2),
+ PLL_RATE(342000000, 57, 1, 2),
+ PLL_RATE(348000000, 58, 1, 2),
+ PLL_RATE(354000000, 59, 1, 2),
+ PLL_RATE(360000000, 60, 1, 2),
+ PLL_RATE(366000000, 61, 1, 2),
+ PLL_RATE(372000000, 62, 1, 2),
+ PLL_RATE(378000000, 63, 1, 2),
+ PLL_RATE(384000000, 64, 1, 2),
+ PLL_RATE(390000000, 65, 1, 3),
+ PLL_RATE(396000000, 66, 1, 3),
+ PLL_RATE(402000000, 67, 1, 3),
+ PLL_RATE(408000000, 68, 1, 3),
+ PLL_RATE(480000000, 40, 1, 1),
+ PLL_RATE(492000000, 41, 1, 1),
+ PLL_RATE(504000000, 42, 1, 1),
+ PLL_RATE(516000000, 43, 1, 1),
+ PLL_RATE(528000000, 44, 1, 1),
+ PLL_RATE(540000000, 45, 1, 1),
+ PLL_RATE(552000000, 46, 1, 1),
+ PLL_RATE(564000000, 47, 1, 1),
+ PLL_RATE(576000000, 48, 1, 1),
+ PLL_RATE(588000000, 49, 1, 1),
+ PLL_RATE(600000000, 50, 1, 1),
+ PLL_RATE(612000000, 51, 1, 1),
+ PLL_RATE(624000000, 52, 1, 1),
+ PLL_RATE(636000000, 53, 1, 1),
+ PLL_RATE(648000000, 54, 1, 1),
+ PLL_RATE(660000000, 55, 1, 1),
+ PLL_RATE(672000000, 56, 1, 1),
+ PLL_RATE(684000000, 57, 1, 1),
+ PLL_RATE(696000000, 58, 1, 1),
+ PLL_RATE(708000000, 59, 1, 1),
+ PLL_RATE(720000000, 60, 1, 1),
+ PLL_RATE(732000000, 61, 1, 1),
+ PLL_RATE(744000000, 62, 1, 1),
+ PLL_RATE(756000000, 63, 1, 1),
+ PLL_RATE(768000000, 64, 1, 1),
+ PLL_RATE(780000000, 65, 1, 1),
+ PLL_RATE(792000000, 66, 1, 1),
+ PLL_RATE(804000000, 67, 1, 1),
+ PLL_RATE(816000000, 68, 1, 1),
+ PLL_RATE(960000000, 40, 1, 0),
+ PLL_RATE(984000000, 41, 1, 0),
+ PLL_RATE(1008000000, 42, 1, 0),
+ PLL_RATE(1032000000, 43, 1, 0),
+ PLL_RATE(1056000000, 44, 1, 0),
+ PLL_RATE(1080000000, 45, 1, 0),
+ PLL_RATE(1104000000, 46, 1, 0),
+ PLL_RATE(1128000000, 47, 1, 0),
+ PLL_RATE(1152000000, 48, 1, 0),
+ PLL_RATE(1176000000, 49, 1, 0),
+ PLL_RATE(1200000000, 50, 1, 0),
+ PLL_RATE(1224000000, 51, 1, 0),
+ PLL_RATE(1248000000, 52, 1, 0),
+ PLL_RATE(1272000000, 53, 1, 0),
+ PLL_RATE(1296000000, 54, 1, 0),
+ PLL_RATE(1320000000, 55, 1, 0),
+ PLL_RATE(1344000000, 56, 1, 0),
+ PLL_RATE(1368000000, 57, 1, 0),
+ PLL_RATE(1392000000, 58, 1, 0),
+ PLL_RATE(1416000000, 59, 1, 0),
+ PLL_RATE(1440000000, 60, 1, 0),
+ PLL_RATE(1464000000, 61, 1, 0),
+ PLL_RATE(1488000000, 62, 1, 0),
+ PLL_RATE(1512000000, 63, 1, 0),
+ PLL_RATE(1536000000, 64, 1, 0),
+ PLL_RATE(1560000000, 65, 1, 0),
+ PLL_RATE(1584000000, 66, 1, 0),
+ PLL_RATE(1608000000, 67, 1, 0),
+ PLL_RATE(1632000000, 68, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct pll_params_table axg_gp0_params_table[] = {
+ PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
+ PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
+ PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
+ PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
+ PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
+ PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
+};
+
+static struct meson_clk_pll axg_gp0_pll = {
+ .m = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ },
+ .params = {
+ .params_table = axg_gp0_params_table,
+ .params_count = ARRAY_SIZE(axg_gp0_params_table),
+ .no_init_reset = true,
+ .reset_lock_loop = true,
+ },
+ .rate_table = axg_gp0_pll_rate_table,
+ .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll",
+ .ops = &meson_clk_pll_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+
+static struct clk_fixed_factor axg_fclk_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div3 = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div4 = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div5 = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div7 = {
+ .mult = 1,
+ .div = 7,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll0 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 14,
+ .width = 1,
+ },
+ .ssen = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 25,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll1 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 14,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll2 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 14,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll3 = {
+ .sdm = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 12,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 11,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 2,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 0,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+/*
+ * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
+ * and should be modeled with their respective PLLs via the forthcoming
+ * coordinated clock rates feature
+ */
+static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
+static const char * const clk81_parent_names[] = {
+ "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
+ "fclk_div3", "fclk_div5"
+};
+
+static struct clk_mux axg_mpeg_clk_sel = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 12,
+ .flags = CLK_MUX_READ_ONLY,
+ .table = mux_table_clk81,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpeg_clk_sel",
+ .ops = &clk_mux_ro_ops,
+ .parent_names = clk81_parent_names,
+ .num_parents = ARRAY_SIZE(clk81_parent_names),
+ },
+};
+
+static struct clk_divider axg_mpeg_clk_div = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpeg_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "mpeg_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_clk81 = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .bit_idx = 7,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "clk81",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "mpeg_clk_div" },
+ .num_parents = 1,
+ .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+ },
+};
+
+static const char * const axg_sd_emmc_clk0_parent_names[] = {
+ "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
+
+ /*
+ * Following these parent clocks, we should also have had mpll2, mpll3
+ * and gp0_pll but these clocks are too precious to be used here. All
+ * the necessary rates for MMC and NAND operation can be acheived using
+ * xtal or fclk_div clocks
+ */
+};
+
+/* SDcard clock */
+static struct clk_mux axg_sd_emmc_b_clk0_sel = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 25,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_clk0_sel",
+ .ops = &clk_mux_ops,
+ .parent_names = axg_sd_emmc_clk0_parent_names,
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider axg_sd_emmc_b_clk0_div = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ .lock = &meson_clk_lock,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_clk0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_sd_emmc_b_clk0 = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .bit_idx = 23,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_b_clk0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* EMMC/NAND clock */
+static struct clk_mux axg_sd_emmc_c_clk0_sel = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 9,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_clk0_sel",
+ .ops = &clk_mux_ops,
+ .parent_names = axg_sd_emmc_clk0_parent_names,
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider axg_sd_emmc_c_clk0_div = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &meson_clk_lock,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_clk0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_sd_emmc_c_clk0 = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .bit_idx = 7,
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_c_clk0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* Everything Else (EE) domain gates */
+static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
+static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
+static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
+static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
+static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
+static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
+static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
+static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
+static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
+static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
+static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
+static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
+static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
+static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
+static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
+static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
+static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
+static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
+static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
+static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
+
+static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
+static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
+static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
+static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
+static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
+static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
+static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
+static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
+static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
+static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
+static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
+
+static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
+static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
+static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
+static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
+static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
+static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
+static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
+static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
+
+/* Always On (AO) domain gates */
+
+static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
+static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
+static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
+static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
+static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
+
+/* Array of all clocks provided by this provider */
+
+static struct clk_hw_onecell_data axg_hw_onecell_data = {
+ .hws = {
+ [CLKID_SYS_PLL] = &axg_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &axg_clk81.hw,
+ [CLKID_MPLL0] = &axg_mpll0.hw,
+ [CLKID_MPLL1] = &axg_mpll1.hw,
+ [CLKID_MPLL2] = &axg_mpll2.hw,
+ [CLKID_MPLL3] = &axg_mpll3.hw,
+ [CLKID_DDR] = &axg_ddr.hw,
+ [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
+ [CLKID_ISA] = &axg_isa.hw,
+ [CLKID_PL301] = &axg_pl301.hw,
+ [CLKID_PERIPHS] = &axg_periphs.hw,
+ [CLKID_SPICC0] = &axg_spicc_0.hw,
+ [CLKID_I2C] = &axg_i2c.hw,
+ [CLKID_RNG0] = &axg_rng0.hw,
+ [CLKID_UART0] = &axg_uart0.hw,
+ [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
+ [CLKID_SPICC1] = &axg_spicc_1.hw,
+ [CLKID_PCIE_A] = &axg_pcie_a.hw,
+ [CLKID_PCIE_B] = &axg_pcie_b.hw,
+ [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
+ [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
+ [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
+ [CLKID_DMA] = &axg_dma.hw,
+ [CLKID_SPI] = &axg_spi.hw,
+ [CLKID_AUDIO] = &axg_audio.hw,
+ [CLKID_ETH] = &axg_eth_core.hw,
+ [CLKID_UART1] = &axg_uart1.hw,
+ [CLKID_G2D] = &axg_g2d.hw,
+ [CLKID_USB0] = &axg_usb0.hw,
+ [CLKID_USB1] = &axg_usb1.hw,
+ [CLKID_RESET] = &axg_reset.hw,
+ [CLKID_USB] = &axg_usb_general.hw,
+ [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
+ [CLKID_EFUSE] = &axg_efuse.hw,
+ [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
+ [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
+ [CLKID_GIC] = &axg_gic.hw,
+ [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &axg_ao_iface.hw,
+ [CLKID_AO_I2C] = &axg_ao_i2c.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
+ [NR_CLKS] = NULL,
+ },
+ .num = NR_CLKS,
+};
+
+/* Convenience tables to populate base addresses in .probe */
+
+static struct meson_clk_pll *const axg_clk_plls[] = {
+ &axg_fixed_pll,
+ &axg_sys_pll,
+ &axg_gp0_pll,
+};
+
+static struct meson_clk_mpll *const axg_clk_mplls[] = {
+ &axg_mpll0,
+ &axg_mpll1,
+ &axg_mpll2,
+ &axg_mpll3,
+};
+
+static struct clk_gate *const axg_clk_gates[] = {
+ &axg_clk81,
+ &axg_ddr,
+ &axg_audio_locker,
+ &axg_mipi_dsi_host,
+ &axg_isa,
+ &axg_pl301,
+ &axg_periphs,
+ &axg_spicc_0,
+ &axg_i2c,
+ &axg_rng0,
+ &axg_uart0,
+ &axg_mipi_dsi_phy,
+ &axg_spicc_1,
+ &axg_pcie_a,
+ &axg_pcie_b,
+ &axg_hiu_reg,
+ &axg_assist_misc,
+ &axg_emmc_b,
+ &axg_emmc_c,
+ &axg_dma,
+ &axg_spi,
+ &axg_audio,
+ &axg_eth_core,
+ &axg_uart1,
+ &axg_g2d,
+ &axg_usb0,
+ &axg_usb1,
+ &axg_reset,
+ &axg_usb_general,
+ &axg_ahb_arb0,
+ &axg_efuse,
+ &axg_boot_rom,
+ &axg_ahb_data_bus,
+ &axg_ahb_ctrl_bus,
+ &axg_usb1_to_ddr,
+ &axg_usb0_to_ddr,
+ &axg_mmc_pclk,
+ &axg_vpu_intr,
+ &axg_sec_ahb_ahb3_bridge,
+ &axg_gic,
+ &axg_ao_media_cpu,
+ &axg_ao_ahb_sram,
+ &axg_ao_ahb_bus,
+ &axg_ao_iface,
+ &axg_ao_i2c,
+ &axg_sd_emmc_b_clk0,
+ &axg_sd_emmc_c_clk0,
+};
+
+static struct clk_mux *const axg_clk_muxes[] = {
+ &axg_mpeg_clk_sel,
+ &axg_sd_emmc_b_clk0_sel,
+ &axg_sd_emmc_c_clk0_sel,
+};
+
+static struct clk_divider *const axg_clk_dividers[] = {
+ &axg_mpeg_clk_div,
+ &axg_sd_emmc_b_clk0_div,
+ &axg_sd_emmc_c_clk0_div,
+};
+
+struct clkc_data {
+ struct clk_gate *const *clk_gates;
+ unsigned int clk_gates_count;
+ struct meson_clk_mpll *const *clk_mplls;
+ unsigned int clk_mplls_count;
+ struct meson_clk_pll *const *clk_plls;
+ unsigned int clk_plls_count;
+ struct clk_mux *const *clk_muxes;
+ unsigned int clk_muxes_count;
+ struct clk_divider *const *clk_dividers;
+ unsigned int clk_dividers_count;
+ struct clk_hw_onecell_data *hw_onecell_data;
+};
+
+static const struct clkc_data axg_clkc_data = {
+ .clk_gates = axg_clk_gates,
+ .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
+ .clk_mplls = axg_clk_mplls,
+ .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
+ .clk_plls = axg_clk_plls,
+ .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
+ .clk_muxes = axg_clk_muxes,
+ .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
+ .clk_dividers = axg_clk_dividers,
+ .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
+ .hw_onecell_data = &axg_hw_onecell_data,
+};
+
+static const struct of_device_id clkc_match_table[] = {
+ { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
+ {}
+};
+
+static int axg_clkc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct clkc_data *clkc_data;
+ struct resource *res;
+ void __iomem *clk_base;
+ int ret, clkid, i;
+
+ clkc_data = of_device_get_match_data(&pdev->dev);
+ if (!clkc_data)
+ return -EINVAL;
+
+ /* Generic clocks and PLLs */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+ clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!clk_base) {
+ dev_err(&pdev->dev, "Unable to map clk base\n");
+ return -ENXIO;
+ }
+
+ /* Populate base address for PLLs */
+ for (i = 0; i < clkc_data->clk_plls_count; i++)
+ clkc_data->clk_plls[i]->base = clk_base;
+
+ /* Populate base address for MPLLs */
+ for (i = 0; i < clkc_data->clk_mplls_count; i++)
+ clkc_data->clk_mplls[i]->base = clk_base;
+
+ /* Populate base address for gates */
+ for (i = 0; i < clkc_data->clk_gates_count; i++)
+ clkc_data->clk_gates[i]->reg = clk_base +
+ (u64)clkc_data->clk_gates[i]->reg;
+
+ /* Populate base address for muxes */
+ for (i = 0; i < clkc_data->clk_muxes_count; i++)
+ clkc_data->clk_muxes[i]->reg = clk_base +
+ (u64)clkc_data->clk_muxes[i]->reg;
+
+ /* Populate base address for dividers */
+ for (i = 0; i < clkc_data->clk_dividers_count; i++)
+ clkc_data->clk_dividers[i]->reg = clk_base +
+ (u64)clkc_data->clk_dividers[i]->reg;
+
+ for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
+ /* array might be sparse */
+ if (!clkc_data->hw_onecell_data->hws[clkid])
+ continue;
+
+ ret = devm_clk_hw_register(dev,
+ clkc_data->hw_onecell_data->hws[clkid]);
+ if (ret) {
+ dev_err(&pdev->dev, "Clock registration failed\n");
+ return ret;
+ }
+ }
+
+ return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ clkc_data->hw_onecell_data);
+}
+
+static struct platform_driver axg_driver = {
+ .probe = axg_clkc_probe,
+ .driver = {
+ .name = "axg-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+builtin_platform_driver(axg_driver);
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
new file mode 100644
index 000000000000..ce0bafdb6b28
--- /dev/null
+++ b/drivers/clk/meson/axg.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 AmLogic, Inc.
+ * Author: Michael Turquette <mturquette@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ *
+ */
+#ifndef __AXG_H
+#define __AXG_H
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet must be multiplied by 4 before
+ * adding them to the base address to get the right value.
+ */
+#define HHI_GP0_PLL_CNTL 0x40
+#define HHI_GP0_PLL_CNTL2 0x44
+#define HHI_GP0_PLL_CNTL3 0x48
+#define HHI_GP0_PLL_CNTL4 0x4c
+#define HHI_GP0_PLL_CNTL5 0x50
+#define HHI_GP0_PLL_STS 0x54
+#define HHI_GP0_PLL_CNTL1 0x58
+#define HHI_HIFI_PLL_CNTL 0x80
+#define HHI_HIFI_PLL_CNTL2 0x84
+#define HHI_HIFI_PLL_CNTL3 0x88
+#define HHI_HIFI_PLL_CNTL4 0x8C
+#define HHI_HIFI_PLL_CNTL5 0x90
+#define HHI_HIFI_PLL_STS 0x94
+#define HHI_HIFI_PLL_CNTL1 0x98
+
+#define HHI_XTAL_DIVN_CNTL 0xbc
+#define HHI_GCLK2_MPEG0 0xc0
+#define HHI_GCLK2_MPEG1 0xc4
+#define HHI_GCLK2_MPEG2 0xc8
+#define HHI_GCLK2_OTHER 0xd0
+#define HHI_GCLK2_AO 0xd4
+#define HHI_PCIE_PLL_CNTL 0xd8
+#define HHI_PCIE_PLL_CNTL1 0xdC
+#define HHI_PCIE_PLL_CNTL2 0xe0
+#define HHI_PCIE_PLL_CNTL3 0xe4
+#define HHI_PCIE_PLL_CNTL4 0xe8
+#define HHI_PCIE_PLL_CNTL5 0xec
+#define HHI_PCIE_PLL_CNTL6 0xf0
+#define HHI_PCIE_PLL_STS 0xf4
+
+#define HHI_MEM_PD_REG0 0x100
+#define HHI_VPU_MEM_PD_REG0 0x104
+#define HHI_VIID_CLK_DIV 0x128
+#define HHI_VIID_CLK_CNTL 0x12c
+
+#define HHI_GCLK_MPEG0 0x140
+#define HHI_GCLK_MPEG1 0x144
+#define HHI_GCLK_MPEG2 0x148
+#define HHI_GCLK_OTHER 0x150
+#define HHI_GCLK_AO 0x154
+#define HHI_SYS_CPU_CLK_CNTL1 0x15c
+#define HHI_SYS_CPU_RESET_CNTL 0x160
+#define HHI_VID_CLK_DIV 0x164
+#define HHI_SPICC_HCLK_CNTL 0x168
+
+#define HHI_MPEG_CLK_CNTL 0x174
+#define HHI_VID_CLK_CNTL 0x17c
+#define HHI_TS_CLK_CNTL 0x190
+#define HHI_VID_CLK_CNTL2 0x194
+#define HHI_SYS_CPU_CLK_CNTL0 0x19c
+#define HHI_VID_PLL_CLK_DIV 0x1a0
+#define HHI_VPU_CLK_CNTL 0x1bC
+
+#define HHI_VAPBCLK_CNTL 0x1F4
+
+#define HHI_GEN_CLK_CNTL 0x228
+
+#define HHI_VDIN_MEAS_CLK_CNTL 0x250
+#define HHI_NAND_CLK_CNTL 0x25C
+#define HHI_SD_EMMC_CLK_CNTL 0x264
+
+#define HHI_MPLL_CNTL 0x280
+#define HHI_MPLL_CNTL2 0x284
+#define HHI_MPLL_CNTL3 0x288
+#define HHI_MPLL_CNTL4 0x28C
+#define HHI_MPLL_CNTL5 0x290
+#define HHI_MPLL_CNTL6 0x294
+#define HHI_MPLL_CNTL7 0x298
+#define HHI_MPLL_CNTL8 0x29C
+#define HHI_MPLL_CNTL9 0x2A0
+#define HHI_MPLL_CNTL10 0x2A4
+
+#define HHI_MPLL3_CNTL0 0x2E0
+#define HHI_MPLL3_CNTL1 0x2E4
+#define HHI_PLL_TOP_MISC 0x2E8
+
+#define HHI_SYS_PLL_CNTL1 0x2FC
+#define HHI_SYS_PLL_CNTL 0x300
+#define HHI_SYS_PLL_CNTL2 0x304
+#define HHI_SYS_PLL_CNTL3 0x308
+#define HHI_SYS_PLL_CNTL4 0x30c
+#define HHI_SYS_PLL_CNTL5 0x310
+#define HHI_SYS_PLL_STS 0x314
+#define HHI_DPLL_TOP_I 0x318
+#define HHI_DPLL_TOP2_I 0x31C
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_MPEG_SEL 8
+#define CLKID_MPEG_DIV 9
+#define CLKID_SD_EMMC_B_CLK0_SEL 61
+#define CLKID_SD_EMMC_B_CLK0_DIV 62
+#define CLKID_SD_EMMC_C_CLK0_SEL 63
+#define CLKID_SD_EMMC_C_CLK0_DIV 64
+
+#define NR_CLKS 65
+
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/axg-clkc.h>
+
+#endif /* __AXG_H */
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 44a5a535ca63..5144360e2c80 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -98,7 +98,7 @@ static void params_from_rate(unsigned long requested_rate,
*sdm = SDM_DEN - 1;
} else {
*n2 = div;
- *sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
+ *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
}
}
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 1629da9b4141..c2ff0520ce53 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -134,7 +134,7 @@ struct meson_clk_audio_divider {
struct clk_gate _name = { \
.reg = (void __iomem *) _reg, \
.bit_idx = (_bit), \
- .lock = &clk_lock, \
+ .lock = &meson_clk_lock, \
.hw.init = &(struct clk_init_data) { \
.name = #_name, \
.ops = &clk_gate_ops, \
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index ae385310e980..af24455af5b4 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -27,7 +27,7 @@
#include "clkc.h"
#include "gxbb.h"
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_rate_table sys_pll_rate_table[] = {
PLL_RATE(24000000, 56, 1, 2),
@@ -294,7 +294,7 @@ static struct meson_clk_pll gxbb_fixed_pll = {
.shift = 16,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -330,7 +330,7 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
.shift = 22,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -358,7 +358,7 @@ static struct meson_clk_pll gxbb_sys_pll = {
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -399,7 +399,7 @@ static struct meson_clk_pll gxbb_gp0_pll = {
},
.rate_table = gxbb_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = &meson_clk_pll_ops,
@@ -442,7 +442,7 @@ static struct meson_clk_pll gxl_gp0_pll = {
},
.rate_table = gxl_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = &meson_clk_pll_ops,
@@ -533,7 +533,7 @@ static struct meson_clk_mpll gxbb_mpll0 = {
.shift = 25,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &meson_clk_mpll_ops,
@@ -563,7 +563,7 @@ static struct meson_clk_mpll gxbb_mpll1 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &meson_clk_mpll_ops,
@@ -593,7 +593,7 @@ static struct meson_clk_mpll gxbb_mpll2 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &meson_clk_mpll_ops,
@@ -620,7 +620,7 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = &clk_mux_ro_ops,
@@ -639,7 +639,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = &clk_divider_ops,
@@ -653,7 +653,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
static struct clk_gate gxbb_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
@@ -667,7 +667,7 @@ static struct clk_mux gxbb_sar_adc_clk_sel = {
.reg = (void *)HHI_SAR_CLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk_sel",
.ops = &clk_mux_ops,
@@ -681,7 +681,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
.reg = (void *)HHI_SAR_CLK_CNTL,
.shift = 0,
.width = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk_div",
.ops = &clk_divider_ops,
@@ -693,7 +693,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
static struct clk_gate gxbb_sar_adc_clk = {
.reg = (void *)HHI_SAR_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk",
.ops = &clk_gate_ops,
@@ -719,7 +719,7 @@ static struct clk_mux gxbb_mali_0_sel = {
.mask = 0x7,
.shift = 9,
.table = mux_table_mali_0_1,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0_sel",
.ops = &clk_mux_ops,
@@ -738,7 +738,7 @@ static struct clk_divider gxbb_mali_0_div = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0_div",
.ops = &clk_divider_ops,
@@ -751,7 +751,7 @@ static struct clk_divider gxbb_mali_0_div = {
static struct clk_gate gxbb_mali_0 = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0",
.ops = &clk_gate_ops,
@@ -766,7 +766,7 @@ static struct clk_mux gxbb_mali_1_sel = {
.mask = 0x7,
.shift = 25,
.table = mux_table_mali_0_1,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1_sel",
.ops = &clk_mux_ops,
@@ -785,7 +785,7 @@ static struct clk_divider gxbb_mali_1_div = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1_div",
.ops = &clk_divider_ops,
@@ -798,7 +798,7 @@ static struct clk_divider gxbb_mali_1_div = {
static struct clk_gate gxbb_mali_1 = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1",
.ops = &clk_gate_ops,
@@ -818,7 +818,7 @@ static struct clk_mux gxbb_mali = {
.mask = 1,
.shift = 31,
.table = mux_table_mali,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali",
.ops = &clk_mux_ops,
@@ -834,7 +834,7 @@ static struct clk_mux gxbb_cts_amclk_sel = {
.shift = 9,
/* Default parent unknown (register reset value: 0) */
.table = (u32[]){ 1, 2, 3 },
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk_sel",
.ops = &clk_mux_ops,
@@ -851,7 +851,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
.width = 8,
},
.flags = CLK_DIVIDER_ROUND_CLOSEST,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk_div",
.ops = &meson_clk_audio_divider_ops,
@@ -864,7 +864,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
static struct clk_gate gxbb_cts_amclk = {
.reg = (void *) HHI_AUD_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk",
.ops = &clk_gate_ops,
@@ -880,7 +880,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
.shift = 25,
/* Default parent unknown (register reset value: 0) */
.table = (u32[]){ 1, 2, 3 },
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_sel",
.ops = &clk_mux_ops,
@@ -894,7 +894,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.shift = 16,
.width = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_div",
@@ -908,7 +908,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
static struct clk_gate gxbb_cts_mclk_i958 = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958",
.ops = &clk_gate_ops,
@@ -922,7 +922,7 @@ static struct clk_mux gxbb_cts_i958 = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.mask = 0x1,
.shift = 27,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_i958",
.ops = &clk_mux_ops,
@@ -940,7 +940,7 @@ static struct clk_divider gxbb_32k_clk_div = {
.reg = (void *)HHI_32K_CLK_CNTL,
.shift = 0,
.width = 14,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk_div",
.ops = &clk_divider_ops,
@@ -953,7 +953,7 @@ static struct clk_divider gxbb_32k_clk_div = {
static struct clk_gate gxbb_32k_clk = {
.reg = (void *)HHI_32K_CLK_CNTL,
.bit_idx = 15,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk",
.ops = &clk_gate_ops,
@@ -971,7 +971,7 @@ static struct clk_mux gxbb_32k_clk_sel = {
.reg = (void *)HHI_32K_CLK_CNTL,
.mask = 0x3,
.shift = 16,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk_sel",
.ops = &clk_mux_ops,
@@ -997,7 +997,7 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_sel",
.ops = &clk_mux_ops,
@@ -1011,7 +1011,7 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_div",
@@ -1025,23 +1025,13 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
static struct clk_gate gxbb_sd_emmc_a_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_a_clk0",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
.num_parents = 1,
-
- /*
- * FIXME:
- * We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
- * instead of this clock. CCF would gate this on boot, killing
- * the mmc controller. Please remove this flag once DT properly
- * point to this clock instead of xtal
- *
- * Same goes for emmc B and C clocks
- */
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1050,7 +1040,7 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = &clk_mux_ops,
@@ -1064,7 +1054,7 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div",
@@ -1078,13 +1068,13 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
static struct clk_gate gxbb_sd_emmc_b_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 23,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1093,7 +1083,7 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
.reg = (void *)HHI_NAND_CLK_CNTL,
.mask = 0x7,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel",
.ops = &clk_mux_ops,
@@ -1107,7 +1097,7 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
.reg = (void *)HHI_NAND_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_div",
@@ -1121,13 +1111,13 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
static struct clk_gate gxbb_sd_emmc_c_clk0 = {
.reg = (void *)HHI_NAND_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1142,7 +1132,7 @@ static struct clk_mux gxbb_vpu_0_sel = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vpu,
.hw.init = &(struct clk_init_data){
.name = "vpu_0_sel",
@@ -1161,7 +1151,7 @@ static struct clk_divider gxbb_vpu_0_div = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_0_div",
.ops = &clk_divider_ops,
@@ -1174,7 +1164,7 @@ static struct clk_divider gxbb_vpu_0_div = {
static struct clk_gate gxbb_vpu_0 = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_0",
.ops = &clk_gate_ops,
@@ -1188,7 +1178,7 @@ static struct clk_mux gxbb_vpu_1_sel = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vpu,
.hw.init = &(struct clk_init_data){
.name = "vpu_1_sel",
@@ -1207,7 +1197,7 @@ static struct clk_divider gxbb_vpu_1_div = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_1_div",
.ops = &clk_divider_ops,
@@ -1220,7 +1210,7 @@ static struct clk_divider gxbb_vpu_1_div = {
static struct clk_gate gxbb_vpu_1 = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_1",
.ops = &clk_gate_ops,
@@ -1234,7 +1224,7 @@ static struct clk_mux gxbb_vpu = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 1,
.shift = 31,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu",
.ops = &clk_mux_ops,
@@ -1259,7 +1249,7 @@ static struct clk_mux gxbb_vapb_0_sel = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vapb,
.hw.init = &(struct clk_init_data){
.name = "vapb_0_sel",
@@ -1278,7 +1268,7 @@ static struct clk_divider gxbb_vapb_0_div = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_0_div",
.ops = &clk_divider_ops,
@@ -1291,7 +1281,7 @@ static struct clk_divider gxbb_vapb_0_div = {
static struct clk_gate gxbb_vapb_0 = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_0",
.ops = &clk_gate_ops,
@@ -1305,7 +1295,7 @@ static struct clk_mux gxbb_vapb_1_sel = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x3,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vapb,
.hw.init = &(struct clk_init_data){
.name = "vapb_1_sel",
@@ -1324,7 +1314,7 @@ static struct clk_divider gxbb_vapb_1_div = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_1_div",
.ops = &clk_divider_ops,
@@ -1337,7 +1327,7 @@ static struct clk_divider gxbb_vapb_1_div = {
static struct clk_gate gxbb_vapb_1 = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_1",
.ops = &clk_gate_ops,
@@ -1351,7 +1341,7 @@ static struct clk_mux gxbb_vapb_sel = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 1,
.shift = 31,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_sel",
.ops = &clk_mux_ops,
@@ -1368,7 +1358,7 @@ static struct clk_mux gxbb_vapb_sel = {
static struct clk_gate gxbb_vapb = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 30,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb",
.ops = &clk_gate_ops,
@@ -1386,7 +1376,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
-static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
+static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
@@ -1437,7 +1427,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
-static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
+static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 20ab7190d328..3ffea80c1308 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -32,7 +32,7 @@
#include "clkc.h"
#include "meson8b.h"
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
static void __iomem *clk_base;
@@ -136,7 +136,7 @@ static struct meson_clk_pll meson8b_fixed_pll = {
.shift = 16,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -162,7 +162,7 @@ static struct meson_clk_pll meson8b_vid_pll = {
.shift = 16,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vid_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -190,7 +190,7 @@ static struct meson_clk_pll meson8b_sys_pll = {
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = &meson_clk_pll_ops,
@@ -281,7 +281,7 @@ static struct meson_clk_mpll meson8b_mpll0 = {
.shift = 25,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &meson_clk_mpll_ops,
@@ -311,7 +311,7 @@ static struct meson_clk_mpll meson8b_mpll1 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &meson_clk_mpll_ops,
@@ -341,7 +341,7 @@ static struct meson_clk_mpll meson8b_mpll2 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &meson_clk_mpll_ops,
@@ -375,7 +375,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = &clk_mux_ro_ops,
@@ -395,7 +395,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = &clk_divider_ops,
@@ -408,7 +408,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
struct clk_gate meson8b_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
@@ -773,7 +773,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
reset = &meson8b_clk_reset_bits[id];
- spin_lock_irqsave(&clk_lock, flags);
+ spin_lock_irqsave(&meson_clk_lock, flags);
val = readl(meson8b_clk_reset->base + reset->reg);
if (assert)
@@ -782,7 +782,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
val &= ~BIT(reset->bit_idx);
writel(val, meson8b_clk_reset->base + reset->reg);
- spin_unlock_irqrestore(&clk_lock, flags);
+ spin_unlock_irqrestore(&meson_clk_lock, flags);
return 0;
}
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index cecb0fdfaef6..87213ea7fc84 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -21,9 +21,11 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/slab.h>
#define TBG_SEL 0x0
@@ -33,6 +35,26 @@
#define CLK_SEL 0x10
#define CLK_DIS 0x14
+#define LOAD_LEVEL_NR 4
+
+#define ARMADA_37XX_NB_L0L1 0x18
+#define ARMADA_37XX_NB_L2L3 0x1C
+#define ARMADA_37XX_NB_TBG_DIV_OFF 13
+#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
+#define ARMADA_37XX_NB_CLK_SEL_OFF 11
+#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
+#define ARMADA_37XX_NB_TBG_SEL_OFF 9
+#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
+#define ARMADA_37XX_NB_CONFIG_SHIFT 16
+#define ARMADA_37XX_NB_DYN_MOD 0x24
+#define ARMADA_37XX_NB_DFS_EN 31
+#define ARMADA_37XX_NB_CPU_LOAD 0x30
+#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
+#define ARMADA_37XX_DVFS_LOAD_0 0
+#define ARMADA_37XX_DVFS_LOAD_1 1
+#define ARMADA_37XX_DVFS_LOAD_2 2
+#define ARMADA_37XX_DVFS_LOAD_3 3
+
struct clk_periph_driver_data {
struct clk_hw_onecell_data *hw_data;
spinlock_t lock;
@@ -46,7 +68,18 @@ struct clk_double_div {
u8 shift2;
};
+struct clk_pm_cpu {
+ struct clk_hw hw;
+ void __iomem *reg_mux;
+ u8 shift_mux;
+ u32 mask_mux;
+ void __iomem *reg_div;
+ u8 shift_div;
+ struct regmap *nb_pm_base;
+};
+
#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
+#define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
struct clk_periph_data {
const char *name;
@@ -55,6 +88,7 @@ struct clk_periph_data {
struct clk_hw *mux_hw;
struct clk_hw *rate_hw;
struct clk_hw *gate_hw;
+ struct clk_hw *muxrate_hw;
bool is_double_div;
};
@@ -79,7 +113,9 @@ static const struct clk_div_table clk_table2[] = {
{ .val = 1, .div = 4, },
{ .val = 0, .div = 0, }, /* last entry */
};
+
static const struct clk_ops clk_double_div_ops;
+static const struct clk_ops clk_pm_cpu_ops;
#define PERIPH_GATE(_name, _bit) \
struct clk_gate gate_##_name = { \
@@ -121,6 +157,18 @@ struct clk_divider rate_##_name = { \
} \
};
+#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
+struct clk_pm_cpu muxrate_##_name = { \
+ .reg_mux = (void *)TBG_SEL, \
+ .mask_mux = 3, \
+ .shift_mux = _shift1, \
+ .reg_div = (void *)_reg, \
+ .shift_div = _shift2, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_pm_cpu_ops, \
+ } \
+};
+
#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
static PERIPH_GATE(_name, _bit); \
static PERIPH_MUX(_name, _shift); \
@@ -135,10 +183,6 @@ static PERIPH_DIV(_name, _reg, _shift1, _table);
static PERIPH_GATE(_name, _bit); \
static PERIPH_DIV(_name, _reg, _shift, _table);
-#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \
-static PERIPH_MUX(_name, _shift); \
-static PERIPH_DIV(_name, _reg, _shift_div, _table);
-
#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
static PERIPH_MUX(_name, _shift); \
static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
@@ -179,13 +223,12 @@ static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
.rate_hw = &rate_##_name.hw, \
}
-#define REF_CLK_MUX_DIV(_name) \
+#define REF_CLK_PM_CPU(_name) \
{ .name = #_name, \
.parent_names = (const char *[]){ "TBG-A-P", \
"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
.num_parents = 4, \
- .mux_hw = &mux_##_name.hw, \
- .rate_hw = &rate_##_name.hw, \
+ .muxrate_hw = &muxrate_##_name.hw, \
}
#define REF_CLK_MUX_DD(_name) \
@@ -215,9 +258,9 @@ PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
-PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
+static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
-static struct clk_periph_data data_nb[] ={
+static struct clk_periph_data data_nb[] = {
REF_CLK_FULL_DD(mmc),
REF_CLK_FULL_DD(sata_host),
REF_CLK_FULL_DD(sec_at),
@@ -234,7 +277,7 @@ static struct clk_periph_data data_nb[] ={
REF_CLK_FULL(trace),
REF_CLK_FULL(counter),
REF_CLK_FULL_DD(eip97),
- REF_CLK_MUX_DIV(cpu),
+ REF_CLK_PM_CPU(cpu),
{ },
};
@@ -281,7 +324,7 @@ static unsigned int get_div(void __iomem *reg, int shift)
}
static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+ unsigned long parent_rate)
{
struct clk_double_div *double_div = to_clk_double_div(hw);
unsigned int div;
@@ -296,6 +339,222 @@ static const struct clk_ops clk_double_div_ops = {
.recalc_rate = clk_double_div_recalc_rate,
};
+static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
+ unsigned int *reg,
+ unsigned int *offset)
+{
+ if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
+ *reg = ARMADA_37XX_NB_L0L1;
+ else
+ *reg = ARMADA_37XX_NB_L2L3;
+
+ if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
+ load_level == ARMADA_37XX_DVFS_LOAD_2)
+ *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
+}
+
+static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
+{
+ unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
+
+ if (IS_ERR(base))
+ return false;
+
+ regmap_read(base, reg, &val);
+
+ return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
+}
+
+static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
+{
+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
+ unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+ unsigned int load_level, div;
+
+ /*
+ * This function is always called after the function
+ * armada_3700_pm_dvfs_is_enabled, so no need to check again
+ * if the base is valid.
+ */
+ regmap_read(base, reg, &load_level);
+
+ /*
+ * The register and the offset inside this register accessed to
+ * read the current divider depend on the load level
+ */
+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
+ armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
+
+ regmap_read(base, reg, &div);
+
+ return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
+}
+
+static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
+{
+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
+ unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
+ unsigned int load_level, sel;
+
+ /*
+ * This function is always called after the function
+ * armada_3700_pm_dvfs_is_enabled, so no need to check again
+ * if the base is valid
+ */
+ regmap_read(base, reg, &load_level);
+
+ /*
+ * The register and the offset inside this register accessed to
+ * read the current divider depend on the load level
+ */
+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
+ armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
+
+ regmap_read(base, reg, &sel);
+
+ return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
+}
+
+static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ u32 val;
+
+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
+ val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
+ } else {
+ val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
+ val &= pm_cpu->mask_mux;
+ }
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ int load_level;
+
+ /*
+ * We set the clock parent only if the DVFS is available but
+ * not enabled.
+ */
+ if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ /* Set the parent clock for all the load level */
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, mask, val,
+ offset = ARMADA_37XX_NB_TBG_SEL_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
+
+ val = index << offset;
+ mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
+ regmap_update_bits(base, reg, mask, val);
+ }
+ return 0;
+}
+
+static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ unsigned int div;
+
+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
+ div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
+ else
+ div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ unsigned int div = *parent_rate / rate;
+ unsigned int load_level;
+ /* only available when DVFS is enabled */
+ if (!armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
+
+ regmap_read(base, reg, &val);
+
+ val >>= offset;
+ val &= ARMADA_37XX_NB_TBG_DIV_MASK;
+ if (val == div)
+ /*
+ * We found a load level matching the target
+ * divider, switch to this load level and
+ * return.
+ */
+ return *parent_rate / div;
+ }
+
+ /* We didn't find any valid divider */
+ return -EINVAL;
+}
+
+static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ unsigned int div = parent_rate / rate;
+ unsigned int load_level;
+
+ /* only available when DVFS is enabled */
+ if (!armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, mask, val,
+ offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
+
+ regmap_read(base, reg, &val);
+ val >>= offset;
+ val &= ARMADA_37XX_NB_TBG_DIV_MASK;
+
+ if (val == div) {
+ /*
+ * We found a load level matching the target
+ * divider, switch to this load level and
+ * return.
+ */
+ reg = ARMADA_37XX_NB_CPU_LOAD;
+ mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
+ regmap_update_bits(base, reg, mask, load_level);
+
+ return rate;
+ }
+ }
+
+ /* We didn't find any valid divider */
+ return -EINVAL;
+}
+
+static const struct clk_ops clk_pm_cpu_ops = {
+ .get_parent = clk_pm_cpu_get_parent,
+ .set_parent = clk_pm_cpu_set_parent,
+ .round_rate = clk_pm_cpu_round_rate,
+ .set_rate = clk_pm_cpu_set_rate,
+ .recalc_rate = clk_pm_cpu_recalc_rate,
+};
+
static const struct of_device_id armada_3700_periph_clock_of_match[] = {
{ .compatible = "marvell,armada-3700-periph-clock-nb",
.data = data_nb, },
@@ -303,6 +562,7 @@ static const struct of_device_id armada_3700_periph_clock_of_match[] = {
.data = data_sb, },
{ }
};
+
static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
void __iomem *reg, spinlock_t *lock,
struct device *dev, struct clk_hw **hw)
@@ -354,15 +614,31 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
}
}
- *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
- data->num_parents, mux_hw,
- mux_ops, rate_hw, rate_ops,
- gate_hw, gate_ops, CLK_IGNORE_UNUSED);
+ if (data->muxrate_hw) {
+ struct clk_pm_cpu *pmcpu_clk;
+ struct clk_hw *muxrate_hw = data->muxrate_hw;
+ struct regmap *map;
- if (IS_ERR(*hw))
- return PTR_ERR(*hw);
+ pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
+ pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
+ pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
- return 0;
+ mux_hw = muxrate_hw;
+ rate_hw = muxrate_hw;
+ mux_ops = muxrate_hw->init->ops;
+ rate_ops = muxrate_hw->init->ops;
+
+ map = syscon_regmap_lookup_by_compatible(
+ "marvell,armada-3700-nb-pm");
+ pmcpu_clk->nb_pm_base = map;
+ }
+
+ *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
+ data->num_parents, mux_hw,
+ mux_ops, rate_hw, rate_ops,
+ gate_hw, gate_ops, CLK_IGNORE_UNUSED);
+
+ return PTR_ERR_OR_ZERO(*hw);
}
static int armada_3700_periph_clock_probe(struct platform_device *pdev)
@@ -406,12 +682,11 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
if (armada_3700_add_composite_clk(&data[i], reg,
&driver_data->lock, dev, hw))
dev_err(dev, "Can't register periph clock %s\n",
- data[i].name);
-
+ data[i].name);
}
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
- driver_data->hw_data);
+ driver_data->hw_data);
if (ret) {
for (i = 0; i < num_periph; i++)
clk_hw_unregister(driver_data->hw_data->hws[i]);
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 7b359afd620e..f5d815f577e0 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -526,7 +526,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
!(pll_is_valid(parent_rate, 1, 1000000, 20000000)
&& pll_is_valid(cco_rate, 1, 156000000, 320000000)
&& pll_is_valid(ref_rate, 1, 1000000, 27000000)))
- pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu",
+ pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
clk_hw_get_name(hw),
parent_rate, cco_rate, ref_rate);
@@ -956,7 +956,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
val &= div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
- divider->flags);
+ divider->flags, divider->width);
}
static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -1505,7 +1505,7 @@ static void __init lpc32xx_clk_init(struct device_node *np)
return;
}
if (clk_get_rate(clk_32k) != 32768) {
- pr_err("invalid clock rate of external 32KHz oscillator");
+ pr_err("invalid clock rate of external 32KHz oscillator\n");
return;
}
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index 42bdaa772be0..2d126df2bccd 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -329,12 +329,16 @@ static void __init pxa3xx_dummy_clocks_init(void)
static void __init pxa3xx_base_clocks_init(void)
{
+ struct clk *clk;
+
pxa3xx_register_plls();
pxa3xx_register_core();
clk_register_clk_pxa3xx_system_bus();
clk_register_clk_pxa3xx_ac97();
clk_register_clk_pxa3xx_smemc();
- clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0, OSCC, 11, 0, NULL);
+ clk = clk_register_gate(NULL, "CLK_POUT",
+ "osc_13mhz", 0, OSCC, 11, 0, NULL);
+ clk_register_clkdev(clk, "CLK_POUT", NULL);
clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
clk_register_fixed_factor(NULL, "os-timer0",
"osc_13mhz", 0, 1, 4));
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9f6c278deead..fbf4532f94b8 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,27 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
+config QCOM_A53PLL
+ tristate "MSM8916 A53 PLL"
+ depends on COMMON_CLK_QCOM
+ default ARCH_QCOM
+ help
+ Support for the A53 PLL on MSM8916 devices. It provides
+ the CPU with frequencies above 1GHz.
+ Say Y if you want to support higher CPU frequencies on MSM8916
+ devices.
+
+config QCOM_CLK_APCS_MSM8916
+ tristate "MSM8916 APCS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ default ARCH_QCOM
+ help
+ Support for the APCS Clock Controller on msm8916 devices. The
+ APCS is managing the mux and divider which feeds the CPUs.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as msm8916.
+
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
@@ -196,3 +217,12 @@ config MSM_MMCC_8996
Support for the multimedia clock controller on msm8996 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+
+config SPMI_PMIC_CLKDIV
+ tristate "SPMI PMIC clkdiv Support"
+ depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
+ help
+ This driver supports the clkdiv functionality on the Qualcomm
+ Technologies, Inc. SPMI PMIC. It configures the frequency of
+ clkdiv outputs of the PMIC. These clocks are typically wired
+ through alternate functions on GPIO pins.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 26410d31446b..230332cf317e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -10,6 +10,7 @@ clk-qcom-y += clk-rcg2.o
clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
+clk-qcom-y += clk-regmap-mux-div.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
@@ -32,5 +33,8 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
+obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
+obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
new file mode 100644
index 000000000000..45cfc57bff92
--- /dev/null
+++ b/drivers/clk/qcom/a53-pll.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Qualcomm A53 PLL driver
+ *
+ * Copyright (c) 2017, Linaro Limited
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/module.h>
+
+#include "clk-pll.h"
+#include "clk-regmap.h"
+
+static const struct pll_freq_tbl a53pll_freq[] = {
+ { 998400000, 52, 0x0, 0x1, 0 },
+ { 1094400000, 57, 0x0, 0x1, 0 },
+ { 1152000000, 62, 0x0, 0x1, 0 },
+ { 1209600000, 63, 0x0, 0x1, 0 },
+ { 1248000000, 65, 0x0, 0x1, 0 },
+ { 1363200000, 71, 0x0, 0x1, 0 },
+ { 1401600000, 73, 0x0, 0x1, 0 },
+ { }
+};
+
+static const struct regmap_config a53pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io = true,
+};
+
+static int qcom_a53pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct resource *res;
+ struct clk_pll *pll;
+ void __iomem *base;
+ struct clk_init_data init = { };
+ int ret;
+
+ pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ pll->l_reg = 0x04;
+ pll->m_reg = 0x08;
+ pll->n_reg = 0x0c;
+ pll->config_reg = 0x14;
+ pll->mode_reg = 0x00;
+ pll->status_reg = 0x1c;
+ pll->status_bit = 16;
+ pll->freq_tbl = a53pll_freq;
+
+ init.name = "a53pll";
+ init.parent_names = (const char *[]){ "xo" };
+ init.num_parents = 1;
+ init.ops = &clk_pll_sr2_ops;
+ init.flags = CLK_IS_CRITICAL;
+ pll->clkr.hw.init = &init;
+
+ ret = devm_clk_register_regmap(dev, &pll->clkr);
+ if (ret) {
+ dev_err(dev, "failed to register regmap clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ &pll->clkr.hw);
+ if (ret) {
+ dev_err(dev, "failed to add clock provider: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qcom_a53pll_match_table[] = {
+ { .compatible = "qcom,msm8916-a53pll" },
+ { }
+};
+
+static struct platform_driver qcom_a53pll_driver = {
+ .probe = qcom_a53pll_probe,
+ .driver = {
+ .name = "qcom-a53pll",
+ .of_match_table = qcom_a53pll_match_table,
+ },
+};
+module_platform_driver(qcom_a53pll_driver);
+
+MODULE_DESCRIPTION("Qualcomm A53 PLL Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
new file mode 100644
index 000000000000..246957f1a413
--- /dev/null
+++ b/drivers/clk/qcom/apcs-msm8916.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Qualcomm APCS clock controller driver
+ *
+ * Copyright (c) 2017, Linaro Limited
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap.h"
+#include "clk-regmap-mux-div.h"
+
+static const u32 gpll0_a53cc_map[] = { 4, 5 };
+
+static const char * const gpll0_a53cc[] = {
+ "gpll0_vote",
+ "a53pll",
+};
+
+/*
+ * We use the notifier function for switching to a temporary safe configuration
+ * (mux and divider), while the A53 PLL is reconfigured.
+ */
+static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event,
+ void *data)
+{
+ int ret = 0;
+ struct clk_regmap_mux_div *md = container_of(nb,
+ struct clk_regmap_mux_div,
+ clk_nb);
+ if (event == PRE_RATE_CHANGE)
+ /* set the mux and divider to safe frequency (400mhz) */
+ ret = mux_div_set_src_div(md, 4, 3);
+
+ return notifier_from_errno(ret);
+}
+
+static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device *parent = dev->parent;
+ struct clk_regmap_mux_div *a53cc;
+ struct regmap *regmap;
+ struct clk_init_data init = { };
+ int ret;
+
+ regmap = dev_get_regmap(parent, NULL);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL);
+ if (!a53cc)
+ return -ENOMEM;
+
+ init.name = "a53mux";
+ init.parent_names = gpll0_a53cc;
+ init.num_parents = ARRAY_SIZE(gpll0_a53cc);
+ init.ops = &clk_regmap_mux_div_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+
+ a53cc->clkr.hw.init = &init;
+ a53cc->clkr.regmap = regmap;
+ a53cc->reg_offset = 0x50;
+ a53cc->hid_width = 5;
+ a53cc->hid_shift = 0;
+ a53cc->src_width = 3;
+ a53cc->src_shift = 8;
+ a53cc->parent_map = gpll0_a53cc_map;
+
+ a53cc->pclk = devm_clk_get(parent, NULL);
+ if (IS_ERR(a53cc->pclk)) {
+ ret = PTR_ERR(a53cc->pclk);
+ dev_err(dev, "failed to get clk: %d\n", ret);
+ return ret;
+ }
+
+ a53cc->clk_nb.notifier_call = a53cc_notifier_cb;
+ ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
+ if (ret) {
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_clk_register_regmap(dev, &a53cc->clkr);
+ if (ret) {
+ dev_err(dev, "failed to register regmap clock: %d\n", ret);
+ goto err;
+ }
+
+ ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get,
+ &a53cc->clkr.hw);
+ if (ret) {
+ dev_err(dev, "failed to add clock provider: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, a53cc);
+
+ return 0;
+
+err:
+ clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+ return ret;
+}
+
+static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
+{
+ struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
+ struct device *parent = pdev->dev.parent;
+
+ clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+ of_clk_del_provider(parent->of_node);
+
+ return 0;
+}
+
+static struct platform_driver qcom_apcs_msm8916_clk_driver = {
+ .probe = qcom_apcs_msm8916_clk_probe,
+ .remove = qcom_apcs_msm8916_clk_remove,
+ .driver = {
+ .name = "qcom-apcs-msm8916-clk",
+ },
+};
+module_platform_driver(qcom_apcs_msm8916_clk_driver);
+
+MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 47a1da3739ce..6d04cd96482a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -20,7 +20,7 @@
#include "clk-alpha-pll.h"
#include "common.h"
-#define PLL_MODE 0x00
+#define PLL_MODE(p) ((p)->offset + 0x0)
# define PLL_OUTCTRL BIT(0)
# define PLL_BYPASSNL BIT(1)
# define PLL_RESET_N BIT(2)
@@ -32,35 +32,87 @@
# define PLL_VOTE_FSM_ENA BIT(20)
# define PLL_FSM_ENA BIT(20)
# define PLL_VOTE_FSM_RESET BIT(21)
+# define PLL_UPDATE BIT(22)
+# define PLL_UPDATE_BYPASS BIT(23)
# define PLL_OFFLINE_ACK BIT(28)
+# define ALPHA_PLL_ACK_LATCH BIT(29)
# define PLL_ACTIVE_FLAG BIT(30)
# define PLL_LOCK_DET BIT(31)
-#define PLL_L_VAL 0x04
-#define PLL_ALPHA_VAL 0x08
-#define PLL_ALPHA_VAL_U 0x0c
+#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
+#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
+#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
-#define PLL_USER_CTL 0x10
+#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8
-# define PLL_POST_DIV_MASK 0xf
+# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
# define PLL_ALPHA_EN BIT(24)
+# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
# define PLL_VCO_MASK 0x3
-#define PLL_USER_CTL_U 0x14
-
-#define PLL_CONFIG_CTL 0x18
-#define PLL_CONFIG_CTL_U 0x20
-#define PLL_TEST_CTL 0x1c
-#define PLL_TEST_CTL_U 0x20
-#define PLL_STATUS 0x24
+#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
+
+#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
+#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
+#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
+#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
+#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
+
+const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
+ [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_USER_CTL_U] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_TEST_CTL_U] = 0x20,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+ [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL] = 0x14,
+ [PLL_OFF_CONFIG_CTL_U] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_TEST_CTL_U] = 0x20,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+ [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
/*
* Even though 40 bits are present, use only 32 for ease of calculation.
*/
#define ALPHA_REG_BITWIDTH 40
-#define ALPHA_BITWIDTH 32
-#define ALPHA_16BIT_MASK 0xffff
+#define ALPHA_REG_16BIT_WIDTH 16
+#define ALPHA_BITWIDTH 32U
+#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
+
+#define PLL_HUAYRA_M_WIDTH 8
+#define PLL_HUAYRA_M_SHIFT 8
+#define PLL_HUAYRA_M_MASK 0xff
+#define PLL_HUAYRA_N_SHIFT 0
+#define PLL_HUAYRA_N_MASK 0xff
+#define PLL_HUAYRA_ALPHA_WIDTH 16
+
+#define pll_alpha_width(p) \
+ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
+ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
+
+#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll, clkr)
@@ -71,18 +123,17 @@
static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
const char *action)
{
- u32 val, off;
+ u32 val;
int count;
int ret;
const char *name = clk_hw_get_name(&pll->clkr.hw);
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
for (count = 100; count > 0; count--) {
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
if (inverse && !(val & mask))
@@ -109,16 +160,30 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
#define wait_for_pll_offline(pll) \
wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
+#define wait_for_pll_update(pll) \
+ wait_for_pll(pll, PLL_UPDATE, 1, "update")
+
+#define wait_for_pll_update_ack_set(pll) \
+ wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
+
+#define wait_for_pll_update_ack_clear(pll) \
+ wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
+
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, mask;
- u32 off = pll->offset;
- regmap_write(regmap, off + PLL_L_VAL, config->l);
- regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
- regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
- regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
+ regmap_write(regmap, PLL_L_VAL(pll), config->l);
+ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+ regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
+
+ if (pll_has_64bit_config(pll))
+ regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
+ config->config_ctl_hi_val);
+
+ if (pll_alpha_width(pll) > 32)
+ regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
val = config->main_output_mask;
val |= config->aux_output_mask;
@@ -127,6 +192,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->vco_val;
+ val |= config->alpha_en_mask;
+ val |= config->alpha_mode_mask;
mask = config->main_output_mask;
mask |= config->aux_output_mask;
@@ -136,20 +203,19 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
mask |= config->post_div_mask;
mask |= config->vco_mask;
- regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
+ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
if (pll->flags & SUPPORTS_FSM_MODE)
- qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
+ qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -158,7 +224,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
if (pll->flags & SUPPORTS_OFFLINE_REQ)
val &= ~PLL_OFFLINE_REQ;
- ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
+ ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
if (ret)
return ret;
@@ -171,16 +237,15 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
if (pll->flags & SUPPORTS_OFFLINE_REQ) {
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
if (ret)
return;
@@ -191,7 +256,7 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
}
/* Disable hwfsm */
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_FSM_ENA, 0);
if (ret)
return;
@@ -202,11 +267,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
static int pll_is_enabled(struct clk_hw *hw, u32 mask)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -227,12 +291,10 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 val, mask, off;
-
- off = pll->offset;
+ u32 val, mask;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -248,7 +310,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
if ((val & mask) == mask)
return 0;
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_BYPASSNL, PLL_BYPASSNL);
if (ret)
return ret;
@@ -260,7 +322,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
mb();
udelay(5);
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
@@ -269,7 +331,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
if (ret)
return ret;
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OUTCTRL, PLL_OUTCTRL);
/* Ensure that the write above goes through before returning. */
@@ -281,11 +343,9 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 val, mask, off;
-
- off = pll->offset;
+ u32 val, mask;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
@@ -296,23 +356,25 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
}
mask = PLL_OUTCTRL;
- regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
/* Delay of 2 output clock ticks required until output is disabled */
mb();
udelay(1);
mask = PLL_RESET_N | PLL_BYPASSNL;
- regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
}
-static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
+static unsigned long
+alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
{
- return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
+ return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
}
static unsigned long
-alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
+alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
+ u32 alpha_width)
{
u64 remainder;
u64 quotient;
@@ -327,14 +389,15 @@ alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
}
/* Upper ALPHA_BITWIDTH bits of Alpha */
- quotient = remainder << ALPHA_BITWIDTH;
+ quotient = remainder << ALPHA_SHIFT(alpha_width);
+
remainder = do_div(quotient, prate);
if (remainder)
quotient++;
*a = quotient;
- return alpha_pll_calc_rate(prate, *l, *a);
+ return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
}
static const struct pll_vco *
@@ -356,71 +419,138 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
u32 l, low, high, ctl;
u64 a = 0, prate = parent_rate;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 off = pll->offset;
+ u32 alpha_width = pll_alpha_width(pll);
- regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
- regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
if (ctl & PLL_ALPHA_EN) {
- regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
- if (pll->flags & SUPPORTS_16BIT_ALPHA) {
- a = low & ALPHA_16BIT_MASK;
- } else {
- regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
+ if (alpha_width > 32) {
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
&high);
a = (u64)high << 32 | low;
- a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
+ } else {
+ a = low & GENMASK(alpha_width - 1, 0);
}
+
+ if (alpha_width > ALPHA_BITWIDTH)
+ a >>= alpha_width - ALPHA_BITWIDTH;
}
- return alpha_pll_calc_rate(prate, l, a);
+ return alpha_pll_calc_rate(prate, l, a, alpha_width);
}
-static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
+static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
+ int (*is_enabled)(struct clk_hw *))
+{
+ int ret;
+ u32 mode;
+
+ if (!is_enabled(&pll->clkr.hw) ||
+ !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
+ return 0;
+
+ regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
+
+ /* Latch the input to the PLL */
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
+ PLL_UPDATE);
+
+ /* Wait for 2 reference cycle before checking ACK bit */
+ udelay(1);
+
+ /*
+ * PLL will latch the new L, Alpha and freq control word.
+ * PLL will respond by raising PLL_ACK_LATCH output when new programming
+ * has been latched in and PLL is being updated. When
+ * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
+ * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
+ */
+ if (mode & PLL_UPDATE_BYPASS) {
+ ret = wait_for_pll_update_ack_set(pll);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
+ } else {
+ ret = wait_for_pll_update(pll);
+ if (ret)
+ return ret;
+ }
+
+ ret = wait_for_pll_update_ack_clear(pll);
+ if (ret)
+ return ret;
+
+ /* Wait for PLL output to stabilize */
+ udelay(10);
+
+ return 0;
+}
+
+static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate,
+ int (*is_enabled)(struct clk_hw *))
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
const struct pll_vco *vco;
- u32 l, off = pll->offset;
+ u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
- rate = alpha_pll_round_rate(rate, prate, &l, &a);
+ rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
vco = alpha_pll_find_vco(pll, rate);
- if (!vco) {
+ if (pll->vco_table && !vco) {
pr_err("alpha pll not in a valid vco range\n");
return -EINVAL;
}
- regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
- if (pll->flags & SUPPORTS_16BIT_ALPHA) {
- regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
- a & ALPHA_16BIT_MASK);
- } else {
- a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
- regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
+ if (alpha_width > ALPHA_BITWIDTH)
+ a <<= alpha_width - ALPHA_BITWIDTH;
+
+ if (alpha_width > 32)
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
+
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+ if (vco) {
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_VCO_MASK << PLL_VCO_SHIFT,
+ vco->val << PLL_VCO_SHIFT);
}
- regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
- PLL_VCO_MASK << PLL_VCO_SHIFT,
- vco->val << PLL_VCO_SHIFT);
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, PLL_ALPHA_EN);
- regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
- PLL_ALPHA_EN);
+ return clk_alpha_pll_update_latch(pll, is_enabled);
+}
- return 0;
+static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ return __clk_alpha_pll_set_rate(hw, rate, prate,
+ clk_alpha_pll_is_enabled);
+}
+
+static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ return __clk_alpha_pll_set_rate(hw, rate, prate,
+ clk_alpha_pll_hwfsm_is_enabled);
}
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 l;
+ u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
unsigned long min_freq, max_freq;
- rate = alpha_pll_round_rate(rate, *prate, &l, &a);
- if (alpha_pll_find_vco(pll, rate))
+ rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
+ if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
@@ -429,6 +559,158 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
return clamp(rate, min_freq, max_freq);
}
+static unsigned long
+alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
+{
+ /*
+ * a contains 16 bit alpha_val in two’s compliment number in the range
+ * of [-0.5, 0.5).
+ */
+ if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
+ l -= 1;
+
+ return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
+}
+
+static unsigned long
+alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
+ u32 *l, u32 *a)
+{
+ u64 remainder;
+ u64 quotient;
+
+ quotient = rate;
+ remainder = do_div(quotient, prate);
+ *l = quotient;
+
+ if (!remainder) {
+ *a = 0;
+ return rate;
+ }
+
+ quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
+ remainder = do_div(quotient, prate);
+
+ if (remainder)
+ quotient++;
+
+ /*
+ * alpha_val should be in two’s compliment number in the range
+ * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
+ * since alpha value will be subtracted in this case.
+ */
+ if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
+ *l += 1;
+
+ *a = quotient;
+ return alpha_huayra_pll_calc_rate(prate, *l, *a);
+}
+
+static unsigned long
+alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ u64 rate = parent_rate, tmp;
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l, alpha = 0, ctl, alpha_m, alpha_n;
+
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ if (ctl & PLL_ALPHA_EN) {
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
+ /*
+ * Depending upon alpha_mode, it can be treated as M/N value or
+ * as a two’s compliment number. When alpha_mode=1,
+ * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
+ *
+ * Fout=FIN*(L+(M/N))
+ *
+ * M is a signed number (-128 to 127) and N is unsigned
+ * (0 to 255). M/N has to be within +/-0.5.
+ *
+ * When alpha_mode=0, it is a two’s compliment number in the
+ * range [-0.5, 0.5).
+ *
+ * Fout=FIN*(L+(alpha_val)/2^16)
+ *
+ * where alpha_val is two’s compliment number.
+ */
+ if (!(ctl & PLL_ALPHA_MODE))
+ return alpha_huayra_pll_calc_rate(rate, l, alpha);
+
+ alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
+ alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
+
+ rate *= l;
+ tmp = parent_rate;
+ if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
+ alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
+ tmp *= alpha_m;
+ do_div(tmp, alpha_n);
+ rate -= tmp;
+ } else {
+ tmp *= alpha_m;
+ do_div(tmp, alpha_n);
+ rate += tmp;
+ }
+
+ return rate;
+ }
+
+ return alpha_huayra_pll_calc_rate(rate, l, alpha);
+}
+
+static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l, a, ctl, cur_alpha = 0;
+
+ rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
+
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ if (ctl & PLL_ALPHA_EN)
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
+
+ /*
+ * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
+ * without having to go through the power on sequence.
+ */
+ if (clk_alpha_pll_is_enabled(hw)) {
+ if (cur_alpha != a) {
+ pr_err("clock needs to be gated %s\n",
+ clk_hw_get_name(hw));
+ return -EBUSY;
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ /* Ensure that the write above goes to detect L val change. */
+ mb();
+ return wait_for_pll_enable_lock(pll);
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+ if (a == 0)
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, 0x0);
+ else
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
+
+ return 0;
+}
+
+static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 l, a;
+
+ return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+}
+
const struct clk_ops clk_alpha_pll_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
@@ -439,13 +721,23 @@ const struct clk_ops clk_alpha_pll_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
+const struct clk_ops clk_alpha_pll_huayra_ops = {
+ .enable = clk_alpha_pll_enable,
+ .disable = clk_alpha_pll_disable,
+ .is_enabled = clk_alpha_pll_is_enabled,
+ .recalc_rate = alpha_pll_huayra_recalc_rate,
+ .round_rate = alpha_pll_huayra_round_rate,
+ .set_rate = alpha_pll_huayra_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
+
const struct clk_ops clk_alpha_pll_hwfsm_ops = {
.enable = clk_alpha_pll_hwfsm_enable,
.disable = clk_alpha_pll_hwfsm_disable,
.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
- .set_rate = clk_alpha_pll_set_rate,
+ .set_rate = clk_alpha_pll_hwfsm_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -455,10 +747,10 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl;
- regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
ctl >>= PLL_POST_DIV_SHIFT;
- ctl &= PLL_POST_DIV_MASK;
+ ctl &= PLL_POST_DIV_MASK(pll);
return parent_rate >> fls(ctl);
}
@@ -472,16 +764,48 @@ static const struct clk_div_table clk_alpha_div_table[] = {
{ }
};
+static const struct clk_div_table clk_alpha_2bit_div_table[] = {
+ { 0x0, 1 },
+ { 0x1, 2 },
+ { 0x3, 4 },
+ { }
+};
+
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+ const struct clk_div_table *table;
- return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
+ if (pll->width == 2)
+ table = clk_alpha_2bit_div_table;
+ else
+ table = clk_alpha_div_table;
+
+ return divider_round_rate(hw, rate, prate, table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
}
+static long
+clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+ u32 ctl, div;
+
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ ctl >>= PLL_POST_DIV_SHIFT;
+ ctl &= BIT(pll->width) - 1;
+ div = 1 << fls(ctl);
+
+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
+ *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -491,8 +815,8 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
- return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
- PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
+ return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
div << PLL_POST_DIV_SHIFT);
}
@@ -502,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = {
.set_rate = clk_alpha_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
+ .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
+ .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d6e1ee2c7348..7593e8a56cf2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -17,6 +17,30 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
+/* Alpha PLL types */
+enum {
+ CLK_ALPHA_PLL_TYPE_DEFAULT,
+ CLK_ALPHA_PLL_TYPE_HUAYRA,
+ CLK_ALPHA_PLL_TYPE_BRAMMO,
+ CLK_ALPHA_PLL_TYPE_MAX,
+};
+
+enum {
+ PLL_OFF_L_VAL,
+ PLL_OFF_ALPHA_VAL,
+ PLL_OFF_ALPHA_VAL_U,
+ PLL_OFF_USER_CTL,
+ PLL_OFF_USER_CTL_U,
+ PLL_OFF_CONFIG_CTL,
+ PLL_OFF_CONFIG_CTL_U,
+ PLL_OFF_TEST_CTL,
+ PLL_OFF_TEST_CTL_U,
+ PLL_OFF_STATUS,
+ PLL_OFF_MAX_REGS
+};
+
+extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
+
struct pll_vco {
unsigned long min_freq;
unsigned long max_freq;
@@ -27,16 +51,18 @@ struct pll_vco {
* struct clk_alpha_pll - phase locked loop (PLL)
* @offset: base address of registers
* @vco_table: array of VCO settings
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
* @clkr: regmap clock handle
*/
struct clk_alpha_pll {
u32 offset;
+ const u8 *regs;
const struct pll_vco *vco_table;
size_t num_vco;
#define SUPPORTS_OFFLINE_REQ BIT(0)
-#define SUPPORTS_16BIT_ALPHA BIT(1)
#define SUPPORTS_FSM_MODE BIT(2)
+#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
u8 flags;
struct clk_regmap clkr;
@@ -45,12 +71,14 @@ struct clk_alpha_pll {
/**
* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
* @offset: base address of registers
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
* @width: width of post-divider
* @clkr: regmap clock handle
*/
struct clk_alpha_pll_postdiv {
u32 offset;
u8 width;
+ const u8 *regs;
struct clk_regmap clkr;
};
@@ -58,12 +86,15 @@ struct clk_alpha_pll_postdiv {
struct alpha_pll_config {
u32 l;
u32 alpha;
+ u32 alpha_hi;
u32 config_ctl_val;
u32 config_ctl_hi_val;
u32 main_output_mask;
u32 aux_output_mask;
u32 aux2_output_mask;
u32 early_output_mask;
+ u32 alpha_en_mask;
+ u32 alpha_mode_mask;
u32 pre_div_val;
u32 pre_div_mask;
u32 post_div_val;
@@ -75,6 +106,8 @@ struct alpha_pll_config {
extern const struct clk_ops clk_alpha_pll_ops;
extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
+extern const struct clk_ops clk_alpha_pll_huayra_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index a2495457e564..2a7489a84e69 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,16 +26,6 @@ struct freq_tbl {
};
/**
- * struct parent_map - map table for PLL source select configuration values
- * @src: source PLL
- * @cfg: configuration value
- */
-struct parent_map {
- u8 src;
- u8 cfg;
-};
-
-/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
* @mnctr_reset_bit: bit to assert mn counter reset
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
index 53484912301e..4e9b8c2c8980 100644
--- a/drivers/clk/qcom/clk-regmap-divider.c
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -23,6 +23,29 @@ static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
}
+static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_regmap_div *divider = to_clk_regmap_div(hw);
+ struct clk_regmap *clkr = &divider->clkr;
+ u32 div;
+ struct clk_hw *hw_parent = clk_hw_get_parent(hw);
+
+ regmap_read(clkr->regmap, divider->reg, &div);
+ div >>= divider->shift;
+ div &= BIT(divider->width) - 1;
+ div += 1;
+
+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
+ if (!hw_parent)
+ return -EINVAL;
+
+ *prate = clk_hw_round_rate(hw_parent, rate * div);
+ }
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
static long div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
@@ -59,7 +82,7 @@ static unsigned long div_recalc_rate(struct clk_hw *hw,
div &= BIT(divider->width) - 1;
return divider_recalc_rate(hw, parent_rate, div, NULL,
- CLK_DIVIDER_ROUND_CLOSEST);
+ CLK_DIVIDER_ROUND_CLOSEST, divider->width);
}
const struct clk_ops clk_regmap_div_ops = {
@@ -68,3 +91,9 @@ const struct clk_ops clk_regmap_div_ops = {
.recalc_rate = div_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
+
+const struct clk_ops clk_regmap_div_ro_ops = {
+ .round_rate = div_round_ro_rate,
+ .recalc_rate = div_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-regmap-divider.h
index fc4492e3a827..8c39c2703caf 100644
--- a/drivers/clk/qcom/clk-regmap-divider.h
+++ b/drivers/clk/qcom/clk-regmap-divider.h
@@ -25,5 +25,6 @@ struct clk_regmap_div {
};
extern const struct clk_ops clk_regmap_div_ops;
+extern const struct clk_ops clk_regmap_div_ro_ops;
#endif
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c
new file mode 100644
index 000000000000..6044839da85a
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap-mux-div.h"
+
+#define CMD_RCGR 0x0
+#define CMD_RCGR_UPDATE BIT(0)
+#define CMD_RCGR_DIRTY_CFG BIT(4)
+#define CMD_RCGR_ROOT_OFF BIT(31)
+#define CFG_RCGR 0x4
+
+#define to_clk_regmap_mux_div(_hw) \
+ container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
+
+int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
+{
+ int ret, count;
+ u32 val, mask;
+ const char *name = clk_hw_get_name(&md->clkr.hw);
+
+ val = (div << md->hid_shift) | (src << md->src_shift);
+ mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
+ ((BIT(md->src_width) - 1) << md->src_shift);
+
+ ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
+ mask, val);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+ CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
+ if (ret)
+ return ret;
+
+ /* Wait for update to take effect */
+ for (count = 500; count > 0; count--) {
+ ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+ &val);
+ if (ret)
+ return ret;
+ if (!(val & CMD_RCGR_UPDATE))
+ return 0;
+ udelay(1);
+ }
+
+ pr_err("%s: RCG did not update its configuration", name);
+ return -EBUSY;
+}
+EXPORT_SYMBOL_GPL(mux_div_set_src_div);
+
+static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
+ u32 *div)
+{
+ u32 val, d, s;
+ const char *name = clk_hw_get_name(&md->clkr.hw);
+
+ regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
+
+ if (val & CMD_RCGR_DIRTY_CFG) {
+ pr_err("%s: RCG configuration is pending\n", name);
+ return;
+ }
+
+ regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
+ s = (val >> md->src_shift);
+ s &= BIT(md->src_width) - 1;
+ *src = s;
+
+ d = (val >> md->hid_shift);
+ d &= BIT(md->hid_width) - 1;
+ *div = d;
+}
+
+static inline bool is_better_rate(unsigned long req, unsigned long best,
+ unsigned long new)
+{
+ return (req <= new && new < best) || (best < req && best < new);
+}
+
+static int mux_div_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ unsigned int i, div, max_div;
+ unsigned long actual_rate, best_rate = 0;
+ unsigned long req_rate = req->rate;
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ max_div = BIT(md->hid_width) - 1;
+ for (div = 1; div < max_div; div++) {
+ parent_rate = mult_frac(req_rate, div, 2);
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
+ actual_rate = mult_frac(parent_rate, 2, div);
+
+ if (is_better_rate(req_rate, best_rate, actual_rate)) {
+ best_rate = actual_rate;
+ req->rate = best_rate;
+ req->best_parent_rate = parent_rate;
+ req->best_parent_hw = parent;
+ }
+
+ if (actual_rate < req_rate || best_rate <= req_rate)
+ break;
+ }
+ }
+
+ if (!best_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate, u32 src)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ int ret;
+ u32 div, max_div, best_src = 0, best_div = 0;
+ unsigned int i;
+ unsigned long actual_rate, best_rate = 0;
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ max_div = BIT(md->hid_width) - 1;
+ for (div = 1; div < max_div; div++) {
+ parent_rate = mult_frac(rate, div, 2);
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
+ actual_rate = mult_frac(parent_rate, 2, div);
+
+ if (is_better_rate(rate, best_rate, actual_rate)) {
+ best_rate = actual_rate;
+ best_src = md->parent_map[i];
+ best_div = div - 1;
+ }
+
+ if (actual_rate < rate || best_rate <= rate)
+ break;
+ }
+ }
+
+ ret = mux_div_set_src_div(md, best_src, best_div);
+ if (!ret) {
+ md->div = best_div;
+ md->src = best_src;
+ }
+
+ return ret;
+}
+
+static u8 mux_div_get_parent(struct clk_hw *hw)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ const char *name = clk_hw_get_name(hw);
+ u32 i, div, src = 0;
+
+ mux_div_get_src_div(md, &src, &div);
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++)
+ if (src == md->parent_map[i])
+ return i;
+
+ pr_err("%s: Can't find parent with src %d\n", name, src);
+ return 0;
+}
+
+static int mux_div_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return mux_div_set_src_div(md, md->parent_map[index], md->div);
+}
+
+static int mux_div_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long prate)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
+}
+
+static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate, u8 index)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return __mux_div_set_rate_and_parent(hw, rate, prate,
+ md->parent_map[index]);
+}
+
+static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ u32 div, src;
+ int i, num_parents = clk_hw_get_num_parents(hw);
+ const char *name = clk_hw_get_name(hw);
+
+ mux_div_get_src_div(md, &src, &div);
+ for (i = 0; i < num_parents; i++)
+ if (src == md->parent_map[i]) {
+ struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(p);
+
+ return mult_frac(parent_rate, 2, div + 1);
+ }
+
+ pr_err("%s: Can't find parent %d\n", name, src);
+ return 0;
+}
+
+const struct clk_ops clk_regmap_mux_div_ops = {
+ .get_parent = mux_div_get_parent,
+ .set_parent = mux_div_set_parent,
+ .set_rate = mux_div_set_rate,
+ .set_rate_and_parent = mux_div_set_rate_and_parent,
+ .determine_rate = mux_div_determine_rate,
+ .recalc_rate = mux_div_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h
new file mode 100644
index 000000000000..6cd6261be7ac
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
+#define __QCOM_CLK_REGMAP_MUX_DIV_H__
+
+#include <linux/clk-provider.h>
+#include "clk-regmap.h"
+
+/**
+ * struct mux_div_clk - combined mux/divider clock
+ * @reg_offset: offset of the mux/divider register
+ * @hid_width: number of bits in half integer divider
+ * @hid_shift: lowest bit of hid value field
+ * @src_width: number of bits in source select
+ * @src_shift: lowest bit of source select field
+ * @div: the divider raw configuration value
+ * @src: the mux index which will be used if the clock is enabled
+ * @parent_map: map from parent_names index to src_sel field
+ * @clkr: handle between common and hardware-specific interfaces
+ * @pclk: the input PLL clock
+ * @clk_nb: clock notifier for rate changes of the input PLL
+ */
+struct clk_regmap_mux_div {
+ u32 reg_offset;
+ u32 hid_width;
+ u32 hid_shift;
+ u32 src_width;
+ u32 src_shift;
+ u32 div;
+ u32 src;
+ const u32 *parent_map;
+ struct clk_regmap clkr;
+ struct clk *pclk;
+ struct notifier_block clk_nb;
+};
+
+extern const struct clk_ops clk_regmap_mux_div_ops;
+extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
+
+#endif
diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c
index cae3071f384c..0f3a1bda3e91 100644
--- a/drivers/clk/qcom/clk-regmap-mux.c
+++ b/drivers/clk/qcom/clk-regmap-mux.c
@@ -35,6 +35,9 @@ static u8 mux_get_parent(struct clk_hw *hw)
val >>= mux->shift;
val &= mask;
+ if (mux->parent_map)
+ return qcom_find_src_index(hw, mux->parent_map, val);
+
return val;
}
@@ -45,6 +48,9 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
+ if (mux->parent_map)
+ index = mux->parent_map[index].cfg;
+
val = index;
val <<= mux->shift;
diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h
index 5cec76154fda..7797cddabe6b 100644
--- a/drivers/clk/qcom/clk-regmap-mux.h
+++ b/drivers/clk/qcom/clk-regmap-mux.h
@@ -16,11 +16,13 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
+#include "common.h"
struct clk_regmap_mux {
u32 reg;
u32 shift;
u32 width;
+ const struct parent_map *parent_map;
struct clk_regmap clkr;
};
diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
new file mode 100644
index 000000000000..8672ab84746f
--- /dev/null
+++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
@@ -0,0 +1,302 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define REG_DIV_CTL1 0x43
+#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)
+
+#define REG_EN_CTL 0x46
+#define REG_EN_MASK BIT(7)
+
+struct clkdiv {
+ struct regmap *regmap;
+ u16 base;
+ spinlock_t lock;
+
+ struct clk_hw hw;
+ unsigned int cxo_period_ns;
+};
+
+static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
+{
+ return container_of(hw, struct clkdiv, hw);
+}
+
+static inline unsigned int div_factor_to_div(unsigned int div_factor)
+{
+ if (!div_factor)
+ div_factor = 1;
+
+ return 1 << (div_factor - 1);
+}
+
+static inline unsigned int div_to_div_factor(unsigned int div)
+{
+ return min(ilog2(div) + 1, 7);
+}
+
+static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
+{
+ unsigned int val = 0;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
+
+ return val & REG_EN_MASK;
+}
+
+static int
+__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
+ unsigned int div_factor)
+{
+ int ret;
+ unsigned int ns = clkdiv->cxo_period_ns;
+ unsigned int div = div_factor_to_div(div_factor);
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
+ REG_EN_MASK, enable ? REG_EN_MASK : 0);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ndelay((2 + 3 * div) * ns);
+ else
+ ndelay(3 * div * ns);
+
+ return 0;
+}
+
+static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
+{
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
+}
+
+static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+}
+
+static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned int div, div_factor;
+
+ div = DIV_ROUND_UP(*parent_rate, rate);
+ div_factor = div_to_div_factor(div);
+ div = div_factor_to_div(div_factor);
+
+ return *parent_rate / div;
+}
+
+static unsigned long
+clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return parent_rate / div_factor_to_div(div_factor);
+}
+
+static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor = div_to_div_factor(parent_rate / rate);
+ unsigned long flags;
+ bool enabled;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
+ if (enabled) {
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ if (ret)
+ goto unlock;
+ }
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
+ DIV_CTL1_DIV_FACTOR_MASK, div_factor);
+ if (ret)
+ goto unlock;
+
+ if (enabled)
+ ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
+ div_factor);
+
+unlock:
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static const struct clk_ops clk_spmi_pmic_div_ops = {
+ .enable = clk_spmi_pmic_div_enable,
+ .disable = clk_spmi_pmic_div_disable,
+ .set_rate = clk_spmi_pmic_div_set_rate,
+ .recalc_rate = clk_spmi_pmic_div_recalc_rate,
+ .round_rate = clk_spmi_pmic_div_round_rate,
+};
+
+struct spmi_pmic_div_clk_cc {
+ int nclks;
+ struct clkdiv clks[];
+};
+
+static struct clk_hw *
+spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct spmi_pmic_div_clk_cc *cc = data;
+ int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
+
+ if (idx < 0 || idx >= cc->nclks) {
+ pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
+ __func__, clkspec->args[0], cc->nclks);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &cc->clks[idx].hw;
+}
+
+static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
+{
+ struct spmi_pmic_div_clk_cc *cc;
+ struct clk_init_data init = {};
+ struct clkdiv *clkdiv;
+ struct clk *cxo;
+ struct regmap *regmap;
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = dev->of_node;
+ const char *parent_name;
+ int nclks, i, ret, cxo_hz;
+ char name[20];
+ u32 start;
+
+ ret = of_property_read_u32(of_node, "reg", &start);
+ if (ret < 0) {
+ dev_err(dev, "reg property reading failed\n");
+ return ret;
+ }
+
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap) {
+ dev_err(dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
+ if (ret < 0) {
+ dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ if (!nclks)
+ return -EINVAL;
+
+ cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks,
+ GFP_KERNEL);
+ if (!cc)
+ return -ENOMEM;
+ cc->nclks = nclks;
+
+ cxo = clk_get(dev, "xo");
+ if (IS_ERR(cxo)) {
+ ret = PTR_ERR(cxo);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get xo clock\n");
+ return ret;
+ }
+ cxo_hz = clk_get_rate(cxo);
+ clk_put(cxo);
+
+ parent_name = of_clk_get_parent_name(of_node, 0);
+ if (!parent_name) {
+ dev_err(dev, "missing parent clock\n");
+ return -ENODEV;
+ }
+
+ init.name = name;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.ops = &clk_spmi_pmic_div_ops;
+
+ for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
+ snprintf(name, sizeof(name), "div_clk%d", i + 1);
+
+ spin_lock_init(&clkdiv[i].lock);
+ clkdiv[i].base = start + i * 0x100;
+ clkdiv[i].regmap = regmap;
+ clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
+ clkdiv[i].hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
+}
+
+static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
+ { .compatible = "qcom,spmi-clkdiv" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
+
+static struct platform_driver spmi_pmic_clkdiv_driver = {
+ .driver = {
+ .name = "qcom,spmi-pmic-clkdiv",
+ .of_match_table = spmi_pmic_clkdiv_match_table,
+ },
+ .probe = spmi_pmic_clkdiv_probe,
+};
+module_platform_driver(spmi_pmic_clkdiv_driver);
+
+MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 23c1927669ba..00196ee15e73 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -20,7 +20,6 @@ struct qcom_reset_map;
struct regmap;
struct freq_tbl;
struct clk_hw;
-struct parent_map;
#define PLL_LOCK_COUNT_SHIFT 8
#define PLL_LOCK_COUNT_MASK 0x3f
@@ -39,6 +38,16 @@ struct qcom_cc_desc {
size_t num_gdscs;
};
+/**
+ * struct parent_map - map table for source select configuration values
+ * @src: source
+ * @cfg: configuration value
+ */
+struct parent_map {
+ u8 src;
+ u8 cfg;
+};
+
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 0f735d37690f..0462f4a8c932 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -28,6 +28,8 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
#include "reset.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -36,6 +38,24 @@ enum {
P_XO,
P_GPLL0,
P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_PCIE20_PHY0_PIPE,
+ P_PCIE20_PHY1_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_USB3PHY_1_PIPE,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_BIAS_PLL,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_UNIPHY1_TX,
+ P_UNIPHY2_RX,
+ P_UNIPHY2_TX,
};
static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
@@ -50,8 +70,345 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_GPLL0_DIV2, 4 },
};
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll2",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_sleep_clk[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll6",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL6, 1 },
+ { P_GPLL0, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
+ "xo",
+ "gpll0_out_main_div2",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 2 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+ "usb3phy_0_cc_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+ "usb3phy_1_cc_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
+ "pcie20_phy0_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
+ "pcie20_phy1_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 3 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
+ "xo",
+ "nss_crypto_pll",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_NSS_CRYPTO_PLL, 1 },
+ { P_GPLL0, 2 },
+};
+
+static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
+ "xo",
+ "ubi32_pll",
+ "gpll0",
+ "gpll2",
+ "gpll4",
+ "gpll6",
+};
+
+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+ { P_GPLL4, 4 },
+ { P_GPLL6, 5 },
+};
+
+static const char * const gcc_xo_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 1 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UNIPHY1_TX, 3 },
+ { P_UNIPHY1_RX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy2_gcc_rx_clk",
+ "uniphy2_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_RX, 1 },
+ { P_UNIPHY2_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy2_gcc_tx_clk",
+ "uniphy2_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_TX, 1 },
+ { P_UNIPHY2_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+ { P_SLEEP_CLK, 6 },
+};
+
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
@@ -82,13 +439,194 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){
"gpll0_main"
},
.num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll2_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll2",
+ .parent_names = (const char *[]){
+ "gpll2_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_names = (const char *[]){
+ "gpll4_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll6_main = {
+ .offset = 0x37000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll6 = {
+ .offset = 0x37000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll6",
+ .parent_names = (const char *[]){
+ "gpll6_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor gpll6_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_out_main_div2",
+ .parent_names = (const char *[]){
+ "gpll6_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll",
+ .parent_names = (const char *[]){
+ "ubi32_pll_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll nss_crypto_pll_main = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv nss_crypto_pll = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll",
+ .parent_names = (const char *[]){
+ "nss_crypto_pll_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
},
};
@@ -428,6 +966,1063 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
},
};
+static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcie0_axi_clk_src = {
+ .cmd_rcgr = 0x75054,
+ .freq_tbl = ftbl_pcie_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_axi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+};
+
+static struct clk_rcg2 pcie0_aux_clk_src = {
+ .cmd_rcgr = 0x75024,
+ .freq_tbl = ftbl_pcie_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie0_pipe_clk_src = {
+ .reg = 0x7501c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie0_pipe_clk_src",
+ .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 pcie1_axi_clk_src = {
+ .cmd_rcgr = 0x76054,
+ .freq_tbl = ftbl_pcie_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_axi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_aux_clk_src = {
+ .cmd_rcgr = 0x76024,
+ .freq_tbl = ftbl_pcie_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie1_pipe_clk_src = {
+ .reg = 0x7601c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie1_pipe_clk_src",
+ .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(24000000, P_GPLL2, 12, 1, 4),
+ F(48000000, P_GPLL2, 12, 1, 2),
+ F(96000000, P_GPLL2, 12, 0, 0),
+ F(177777778, P_GPLL0, 4.5, 0, 0),
+ F(192000000, P_GPLL2, 6, 0, 0),
+ F(384000000, P_GPLL2, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x42004,
+ .freq_tbl = ftbl_sdcc_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ F(308570000, P_GPLL6, 3.5, 0, 0),
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x5d000,
+ .freq_tbl = ftbl_sdcc_ice_core_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x43004,
+ .freq_tbl = ftbl_sdcc_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_master_clk_src[] = {
+ F(80000000, P_GPLL0_DIV2, 5, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(133330000, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb0_master_clk_src = {
+ .cmd_rcgr = 0x3e00c,
+ .freq_tbl = ftbl_usb_master_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_master_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb0_aux_clk_src = {
+ .cmd_rcgr = 0x3e05c,
+ .freq_tbl = ftbl_usb_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(20000000, P_GPLL6, 6, 1, 9),
+ F(60000000, P_GPLL6, 6, 1, 3),
+ { }
+};
+
+static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3e020,
+ .freq_tbl = ftbl_usb_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_mock_utmi_clk_src",
+ .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x3e048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb0_pipe_clk_src",
+ .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 usb1_master_clk_src = {
+ .cmd_rcgr = 0x3f00c,
+ .freq_tbl = ftbl_usb_master_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_master_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb1_aux_clk_src = {
+ .cmd_rcgr = 0x3f05c,
+ .freq_tbl = ftbl_usb_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb1_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3f020,
+ .freq_tbl = ftbl_usb_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_mock_utmi_clk_src",
+ .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb1_pipe_clk_src = {
+ .reg = 0x3f048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb1_pipe_clk_src",
+ .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk_src = {
+ .halt_reg = 0x30018,
+ .clkr = {
+ .enable_reg = 0x30018,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_clk_src",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_div4_clk_src",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0_DIV2, 8, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(133333333, P_GPLL0, 6, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x26004,
+ .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "system_noc_bfdcd_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor system_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "system_noc_clk_src",
+ .parent_names = (const char *[]){
+ "system_noc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ce_clk_src = {
+ .cmd_rcgr = 0x68098,
+ .freq_tbl = ftbl_nss_ce_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ce_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x68088,
+ .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_noc_bfdcd_clk_src",
+ .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor nss_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_noc_clk_src",
+ .parent_names = (const char *[]){
+ "nss_noc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_crypto_clk_src = {
+ .cmd_rcgr = 0x68144,
+ .freq_tbl = ftbl_nss_crypto_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_clk_src",
+ .parent_names = gcc_xo_nss_crypto_pll_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(187200000, P_UBI32_PLL, 8, 0, 0),
+ F(748800000, P_UBI32_PLL, 2, 0, 0),
+ F(1497600000, P_UBI32_PLL, 1, 0, 0),
+ F(1689600000, P_UBI32_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ubi0_clk_src = {
+ .cmd_rcgr = 0x68104,
+ .freq_tbl = ftbl_nss_ubi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_clk_src",
+ .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap_div nss_ubi0_div_clk_src = {
+ .reg = 0x68118,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ubi0_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_ubi1_clk_src = {
+ .cmd_rcgr = 0x68124,
+ .freq_tbl = ftbl_nss_ubi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_clk_src",
+ .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap_div nss_ubi1_div_clk_src = {
+ .reg = 0x68138,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ubi1_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_DIV2, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ubi_mpt_clk_src = {
+ .cmd_rcgr = 0x68090,
+ .freq_tbl = ftbl_ubi_mpt_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi_mpt_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_imem_clk_src = {
+ .cmd_rcgr = 0x68158,
+ .freq_tbl = ftbl_nss_imem_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_imem_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll4,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(300000000, P_BIAS_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ppe_clk_src = {
+ .cmd_rcgr = 0x68080,
+ .freq_tbl = ftbl_nss_ppe_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_clk_src",
+ .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_cdiv_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY0_RX, 5, 0, 0),
+ F(125000000, P_UNIPHY0_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port1_rx_clk_src = {
+ .cmd_rcgr = 0x68020,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port1_rx_div_clk_src = {
+ .reg = 0x68400,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY0_TX, 5, 0, 0),
+ F(125000000, P_UNIPHY0_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port1_tx_clk_src = {
+ .cmd_rcgr = 0x68028,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port1_tx_div_clk_src = {
+ .reg = 0x68404,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port2_rx_clk_src = {
+ .cmd_rcgr = 0x68030,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port2_rx_div_clk_src = {
+ .reg = 0x68410,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port2_tx_clk_src = {
+ .cmd_rcgr = 0x68038,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port2_tx_div_clk_src = {
+ .reg = 0x68414,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port3_rx_clk_src = {
+ .cmd_rcgr = 0x68040,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port3_rx_div_clk_src = {
+ .reg = 0x68420,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port3_tx_clk_src = {
+ .cmd_rcgr = 0x68048,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port3_tx_div_clk_src = {
+ .reg = 0x68424,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port4_rx_clk_src = {
+ .cmd_rcgr = 0x68050,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port4_rx_div_clk_src = {
+ .reg = 0x68430,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port4_tx_clk_src = {
+ .cmd_rcgr = 0x68058,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port4_tx_div_clk_src = {
+ .reg = 0x68434,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY1_RX, 4, 0, 0),
+ F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY1_RX, 2, 0, 0),
+ F(312500000, P_UNIPHY1_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port5_rx_clk_src = {
+ .cmd_rcgr = 0x68060,
+ .freq_tbl = ftbl_nss_port5_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
+ .num_parents = 7,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port5_rx_div_clk_src = {
+ .reg = 0x68440,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY1_TX, 4, 0, 0),
+ F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY1_TX, 2, 0, 0),
+ F(312500000, P_UNIPHY1_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port5_tx_clk_src = {
+ .cmd_rcgr = 0x68068,
+ .freq_tbl = ftbl_nss_port5_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
+ .num_parents = 7,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port5_tx_div_clk_src = {
+ .reg = 0x68444,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY2_RX, 4, 0, 0),
+ F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY2_RX, 2, 0, 0),
+ F(312500000, P_UNIPHY2_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port6_rx_clk_src = {
+ .cmd_rcgr = 0x68070,
+ .freq_tbl = ftbl_nss_port6_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_clk_src",
+ .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port6_rx_div_clk_src = {
+ .reg = 0x68450,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY2_TX, 4, 0, 0),
+ F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY2_TX, 2, 0, 0),
+ F(312500000, P_UNIPHY2_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port6_tx_clk_src = {
+ .cmd_rcgr = 0x68078,
+ .freq_tbl = ftbl_nss_port6_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_clk_src",
+ .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port6_tx_div_clk_src = {
+ .reg = 0x68454,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct freq_tbl ftbl_crypto_clk_src[] = {
+ F(40000000, P_GPLL0_DIV2, 10, 0, 0),
+ F(80000000, P_GPLL0, 10, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .freq_tbl = ftbl_crypto_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "crypto_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gp_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x08004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x09004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x0a004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.clkr = {
@@ -803,14 +2398,1957 @@ static struct clk_branch gcc_qpic_clk = {
},
};
+static struct clk_branch gcc_pcie0_ahb_clk = {
+ .halt_reg = 0x75010,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+ .halt_reg = 0x75014,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_aux_clk",
+ .parent_names = (const char *[]){
+ "pcie0_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+ .halt_reg = 0x75008,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_m_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+ .halt_reg = 0x7500c,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_s_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x75018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x75018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
+ .halt_reg = 0x26048,
+ .clkr = {
+ .enable_reg = 0x26048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie0_axi_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+ .halt_reg = 0x76010,
+ .clkr = {
+ .enable_reg = 0x76010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+ .halt_reg = 0x76014,
+ .clkr = {
+ .enable_reg = 0x76014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_aux_clk",
+ .parent_names = (const char *[]){
+ "pcie1_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+ .halt_reg = 0x76008,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_m_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+ .halt_reg = 0x7600c,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_s_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x76018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x76018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie1_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
+ .halt_reg = 0x2604c,
+ .clkr = {
+ .enable_reg = 0x2604c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie1_axi_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x3e044,
+ .clkr = {
+ .enable_reg = 0x3e044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_aux_clk",
+ .parent_names = (const char *[]){
+ "usb0_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
+ .halt_reg = 0x26040,
+ .clkr = {
+ .enable_reg = 0x26040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb0_axi_clk",
+ .parent_names = (const char *[]){
+ "usb0_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x3e000,
+ .clkr = {
+ .enable_reg = 0x3e000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_master_clk",
+ .parent_names = (const char *[]){
+ "usb0_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x3e008,
+ .clkr = {
+ .enable_reg = 0x3e008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb0_mock_utmi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3e080,
+ .clkr = {
+ .enable_reg = 0x3e080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x3e040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3e040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_names = (const char *[]){
+ "usb0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x3e004,
+ .clkr = {
+ .enable_reg = 0x3e004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_names = (const char *[]){
+ "gcc_sleep_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_aux_clk = {
+ .halt_reg = 0x3f044,
+ .clkr = {
+ .enable_reg = 0x3f044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_aux_clk",
+ .parent_names = (const char *[]){
+ "usb1_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
+ .halt_reg = 0x26044,
+ .clkr = {
+ .enable_reg = 0x26044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb1_axi_clk",
+ .parent_names = (const char *[]){
+ "usb1_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_master_clk = {
+ .halt_reg = 0x3f000,
+ .clkr = {
+ .enable_reg = 0x3f000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_master_clk",
+ .parent_names = (const char *[]){
+ "usb1_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_mock_utmi_clk = {
+ .halt_reg = 0x3f008,
+ .clkr = {
+ .enable_reg = 0x3f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb1_mock_utmi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3f080,
+ .clkr = {
+ .enable_reg = 0x3f080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_phy_cfg_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_pipe_clk = {
+ .halt_reg = 0x3f040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3f040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_pipe_clk",
+ .parent_names = (const char *[]){
+ "usb1_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_sleep_clk = {
+ .halt_reg = 0x3f004,
+ .clkr = {
+ .enable_reg = 0x3f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_sleep_clk",
+ .parent_names = (const char *[]){
+ "gcc_sleep_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x4201c,
+ .clkr = {
+ .enable_reg = 0x4201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x42018,
+ .clkr = {
+ .enable_reg = 0x42018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x5d014,
+ .clkr = {
+ .enable_reg = 0x5d014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x4301c,
+ .clkr = {
+ .enable_reg = 0x4301c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x43018,
+ .clkr = {
+ .enable_reg = 0x43018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_nss_axi_clk = {
+ .halt_reg = 0x1d03c,
+ .clkr = {
+ .enable_reg = 0x1d03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mem_noc_nss_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ce_apb_clk = {
+ .halt_reg = 0x68174,
+ .clkr = {
+ .enable_reg = 0x68174,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_apb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ce_axi_clk = {
+ .halt_reg = 0x68170,
+ .clkr = {
+ .enable_reg = 0x68170,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_cfg_clk = {
+ .halt_reg = 0x68160,
+ .clkr = {
+ .enable_reg = 0x68160,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_cfg_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_crypto_clk = {
+ .halt_reg = 0x68164,
+ .clkr = {
+ .enable_reg = 0x68164,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_crypto_clk",
+ .parent_names = (const char *[]){
+ "nss_crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_csr_clk = {
+ .halt_reg = 0x68318,
+ .clkr = {
+ .enable_reg = 0x68318,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_csr_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_edma_cfg_clk = {
+ .halt_reg = 0x6819c,
+ .clkr = {
+ .enable_reg = 0x6819c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_edma_clk = {
+ .halt_reg = 0x68198,
+ .clkr = {
+ .enable_reg = 0x68198,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_imem_clk = {
+ .halt_reg = 0x68178,
+ .clkr = {
+ .enable_reg = 0x68178,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_imem_clk",
+ .parent_names = (const char *[]){
+ "nss_imem_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_noc_clk = {
+ .halt_reg = 0x68168,
+ .clkr = {
+ .enable_reg = 0x68168,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_noc_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_btq_clk = {
+ .halt_reg = 0x6833c,
+ .clkr = {
+ .enable_reg = 0x6833c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_btq_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_cfg_clk = {
+ .halt_reg = 0x68194,
+ .clkr = {
+ .enable_reg = 0x68194,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_clk = {
+ .halt_reg = 0x68190,
+ .clkr = {
+ .enable_reg = 0x68190,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_ipe_clk = {
+ .halt_reg = 0x68338,
+ .clkr = {
+ .enable_reg = 0x68338,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_ipe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ptp_ref_clk = {
+ .halt_reg = 0x6816c,
+ .clkr = {
+ .enable_reg = 0x6816c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ptp_ref_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_cdiv_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x6830c,
+ .clkr = {
+ .enable_reg = 0x6830c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_apb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x68308,
+ .clkr = {
+ .enable_reg = 0x68308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_crypto_clk = {
+ .halt_reg = 0x68314,
+ .clkr = {
+ .enable_reg = 0x68314,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_crypto_clk",
+ .parent_names = (const char *[]){
+ "nss_crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x68304,
+ .clkr = {
+ .enable_reg = 0x68304,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ppe_clk = {
+ .halt_reg = 0x68300,
+ .clkr = {
+ .enable_reg = 0x68300,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
+ .halt_reg = 0x68180,
+ .clkr = {
+ .enable_reg = 0x68180,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_qosgen_ref_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_clk = {
+ .halt_reg = 0x68188,
+ .clkr = {
+ .enable_reg = 0x68188,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_snoc_clk",
+ .parent_names = (const char *[]){
+ "system_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
+ .halt_reg = 0x68184,
+ .clkr = {
+ .enable_reg = 0x68184,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_timeout_ref_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_div4_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
+ .halt_reg = 0x68270,
+ .clkr = {
+ .enable_reg = 0x68270,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi0_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
+ .halt_reg = 0x68274,
+ .clkr = {
+ .enable_reg = 0x68274,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi1_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_ahb_clk = {
+ .halt_reg = 0x6820c,
+ .clkr = {
+ .enable_reg = 0x6820c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_axi_clk = {
+ .halt_reg = 0x68200,
+ .clkr = {
+ .enable_reg = 0x68200,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_nc_axi_clk = {
+ .halt_reg = 0x68204,
+ .clkr = {
+ .enable_reg = 0x68204,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_nc_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_core_clk = {
+ .halt_reg = 0x68210,
+ .clkr = {
+ .enable_reg = 0x68210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_core_clk",
+ .parent_names = (const char *[]){
+ "nss_ubi0_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_mpt_clk = {
+ .halt_reg = 0x68208,
+ .clkr = {
+ .enable_reg = 0x68208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_mpt_clk",
+ .parent_names = (const char *[]){
+ "ubi_mpt_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_ahb_clk = {
+ .halt_reg = 0x6822c,
+ .clkr = {
+ .enable_reg = 0x6822c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_axi_clk = {
+ .halt_reg = 0x68220,
+ .clkr = {
+ .enable_reg = 0x68220,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_nc_axi_clk = {
+ .halt_reg = 0x68224,
+ .clkr = {
+ .enable_reg = 0x68224,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_nc_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_core_clk = {
+ .halt_reg = 0x68230,
+ .clkr = {
+ .enable_reg = 0x68230,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_core_clk",
+ .parent_names = (const char *[]){
+ "nss_ubi1_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_mpt_clk = {
+ .halt_reg = 0x68228,
+ .clkr = {
+ .enable_reg = 0x68228,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_mpt_clk",
+ .parent_names = (const char *[]){
+ "ubi_mpt_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
+ .halt_reg = 0x56308,
+ .clkr = {
+ .enable_reg = 0x56308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
+ .halt_reg = 0x5630c,
+ .clkr = {
+ .enable_reg = 0x5630c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_ahb_clk = {
+ .halt_reg = 0x58004,
+ .clkr = {
+ .enable_reg = 0x58004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mdio_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_ahb_clk = {
+ .halt_reg = 0x56008,
+ .clkr = {
+ .enable_reg = 0x56008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_sys_clk = {
+ .halt_reg = 0x5600c,
+ .clkr = {
+ .enable_reg = 0x5600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_ahb_clk = {
+ .halt_reg = 0x56108,
+ .clkr = {
+ .enable_reg = 0x56108,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_sys_clk = {
+ .halt_reg = 0x5610c,
+ .clkr = {
+ .enable_reg = 0x5610c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_ahb_clk = {
+ .halt_reg = 0x56208,
+ .clkr = {
+ .enable_reg = 0x56208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_sys_clk = {
+ .halt_reg = 0x5620c,
+ .clkr = {
+ .enable_reg = 0x5620c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port1_rx_clk = {
+ .halt_reg = 0x68240,
+ .clkr = {
+ .enable_reg = 0x68240,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port1_tx_clk = {
+ .halt_reg = 0x68244,
+ .clkr = {
+ .enable_reg = 0x68244,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port2_rx_clk = {
+ .halt_reg = 0x68248,
+ .clkr = {
+ .enable_reg = 0x68248,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port2_tx_clk = {
+ .halt_reg = 0x6824c,
+ .clkr = {
+ .enable_reg = 0x6824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port3_rx_clk = {
+ .halt_reg = 0x68250,
+ .clkr = {
+ .enable_reg = 0x68250,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port3_tx_clk = {
+ .halt_reg = 0x68254,
+ .clkr = {
+ .enable_reg = 0x68254,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port4_rx_clk = {
+ .halt_reg = 0x68258,
+ .clkr = {
+ .enable_reg = 0x68258,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port4_tx_clk = {
+ .halt_reg = 0x6825c,
+ .clkr = {
+ .enable_reg = 0x6825c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port5_rx_clk = {
+ .halt_reg = 0x68260,
+ .clkr = {
+ .enable_reg = 0x68260,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port5_tx_clk = {
+ .halt_reg = 0x68264,
+ .clkr = {
+ .enable_reg = 0x68264,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port6_rx_clk = {
+ .halt_reg = 0x68268,
+ .clkr = {
+ .enable_reg = 0x68268,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port6_tx_clk = {
+ .halt_reg = 0x6826c,
+ .clkr = {
+ .enable_reg = 0x6826c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port1_mac_clk = {
+ .halt_reg = 0x68320,
+ .clkr = {
+ .enable_reg = 0x68320,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port1_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port2_mac_clk = {
+ .halt_reg = 0x68324,
+ .clkr = {
+ .enable_reg = 0x68324,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port2_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port3_mac_clk = {
+ .halt_reg = 0x68328,
+ .clkr = {
+ .enable_reg = 0x68328,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port3_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port4_mac_clk = {
+ .halt_reg = 0x6832c,
+ .clkr = {
+ .enable_reg = 0x6832c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port4_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port5_mac_clk = {
+ .halt_reg = 0x68330,
+ .clkr = {
+ .enable_reg = 0x68330,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port5_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port6_mac_clk = {
+ .halt_reg = 0x68334,
+ .clkr = {
+ .enable_reg = 0x68334,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port6_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port1_rx_clk = {
+ .halt_reg = 0x56010,
+ .clkr = {
+ .enable_reg = 0x56010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port1_tx_clk = {
+ .halt_reg = 0x56014,
+ .clkr = {
+ .enable_reg = 0x56014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port2_rx_clk = {
+ .halt_reg = 0x56018,
+ .clkr = {
+ .enable_reg = 0x56018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port2_tx_clk = {
+ .halt_reg = 0x5601c,
+ .clkr = {
+ .enable_reg = 0x5601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port3_rx_clk = {
+ .halt_reg = 0x56020,
+ .clkr = {
+ .enable_reg = 0x56020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port3_tx_clk = {
+ .halt_reg = 0x56024,
+ .clkr = {
+ .enable_reg = 0x56024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port4_rx_clk = {
+ .halt_reg = 0x56028,
+ .clkr = {
+ .enable_reg = 0x56028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port4_tx_clk = {
+ .halt_reg = 0x5602c,
+ .clkr = {
+ .enable_reg = 0x5602c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port5_rx_clk = {
+ .halt_reg = 0x56030,
+ .clkr = {
+ .enable_reg = 0x56030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port5_tx_clk = {
+ .halt_reg = 0x56034,
+ .clkr = {
+ .enable_reg = 0x56034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_port5_rx_clk = {
+ .halt_reg = 0x56110,
+ .clkr = {
+ .enable_reg = 0x56110,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_port5_tx_clk = {
+ .halt_reg = 0x56114,
+ .clkr = {
+ .enable_reg = 0x56114,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_port6_rx_clk = {
+ .halt_reg = 0x56210,
+ .clkr = {
+ .enable_reg = 0x56210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_port6_tx_clk = {
+ .halt_reg = 0x56214,
+ .clkr = {
+ .enable_reg = 0x56214,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+ .halt_reg = 0x16024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_axi_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_axi_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_clk",
+ .parent_names = (const char *[]){
+ "crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x08000,
+ .clkr = {
+ .enable_reg = 0x08000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x09000,
+ .clkr = {
+ .enable_reg = 0x09000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x0a000,
+ .clkr = {
+ .enable_reg = 0x0a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw,
+ &gpll6_out_main_div2.hw,
&pcnoc_clk_src.hw,
+ &system_noc_clk_src.hw,
+ &gcc_xo_div4_clk_src.hw,
+ &nss_noc_clk_src.hw,
+ &nss_ppe_cdiv_clk_src.hw,
};
static struct clk_regmap *gcc_ipq8074_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [GPLL6_MAIN] = &gpll6_main.clkr,
+ [GPLL6] = &gpll6.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
+ [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -831,6 +4369,63 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
+ [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
+ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
+ [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
+ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
+ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
+ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
+ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+ [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
+ [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
+ [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
+ [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+ [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
+ [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
+ [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
+ [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
+ [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
+ [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
+ [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
+ [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
+ [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
+ [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
+ [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
+ [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
+ [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
+ [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
+ [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
+ [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
+ [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
+ [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
+ [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
+ [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
+ [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
+ [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
+ [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
+ [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
+ [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
+ [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
+ [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
+ [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
+ [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
+ [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
+ [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
+ [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
+ [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
+ [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
@@ -853,6 +4448,119 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
+ [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
+ [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
+ [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
+ [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
+ [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
+ [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
+ [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
+ [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
+ [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
+ [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
+ [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
+ [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
+ [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
+ [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
+ [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
+ [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
+ [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
+ [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
+ [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
+ [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
+ [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
+ [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
+ [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
+ [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
+ [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
+ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
+ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
+ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
+ [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
+ [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
+ [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
+ [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
+ [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
+ [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
+ [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
+ [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
+ [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
+ [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
+ [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
+ [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
+ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
+ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
+ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
+ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
+ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
+ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
+ [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
+ [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
+ [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
+ [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
+ [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
+ [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
+ [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
+ [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
+ [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
+ [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
+ [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
+ [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
+ [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
+ [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
+ [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
+ [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
+ [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
+ [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
+ [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
+ [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
+ [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
+ [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
+ [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
+ [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
+ [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -945,6 +4653,48 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
[GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
+ [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
+ [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
+ [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
+ [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
+ [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
+ [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
+ [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
+ [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
+ [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
+ [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
+ [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
+ [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
+ [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
+ [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
+ [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
+ [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
+ [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
+ [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
+ [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
+ [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
+ [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
+ [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
+ [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
+ [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
+ [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
+ [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
+ [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
+ [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
+ [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
+ [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
+ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
+ [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
+ [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
+ [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
+ [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
+ [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
+ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
+ [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
+ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
};
static const struct of_device_id gcc_ipq8074_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 3410ee68d4bc..d6c7f50ba86a 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1259,20 +1259,25 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
};
static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
+ F(128000, P_XO, 10, 1, 15),
F(256000, P_XO, 5, 1, 15),
+ F(384000, P_XO, 5, 1, 10),
F(512000, P_XO, 5, 2, 15),
+ F(576000, P_XO, 5, 3, 20),
F(705600, P_GPLL1, 16, 1, 80),
F(768000, P_XO, 5, 1, 5),
F(800000, P_XO, 5, 5, 24),
- F(1024000, P_GPLL1, 14, 1, 63),
+ F(1024000, P_XO, 5, 4, 15),
F(1152000, P_XO, 1, 3, 50),
F(1411200, P_GPLL1, 16, 1, 40),
F(1536000, P_XO, 1, 2, 25),
F(1600000, P_XO, 12, 0, 0),
- F(2048000, P_GPLL1, 9, 1, 49),
+ F(1728000, P_XO, 5, 9, 20),
+ F(2048000, P_XO, 5, 8, 15),
+ F(2304000, P_XO, 5, 3, 5),
F(2400000, P_XO, 8, 0, 0),
F(2822400, P_GPLL1, 16, 1, 20),
- F(3072000, P_GPLL1, 14, 1, 21),
+ F(3072000, P_XO, 5, 4, 5),
F(4096000, P_GPLL1, 9, 2, 49),
F(4800000, P_XO, 4, 0, 0),
F(5644800, P_GPLL1, 16, 1, 10),
@@ -1431,6 +1436,7 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {
static const struct freq_tbl ftbl_codec_clk[] = {
F(9600000, P_XO, 2, 0, 0),
+ F(12288000, P_XO, 1, 16, 25),
F(19200000, P_XO, 1, 0, 0),
F(11289600, P_EXT_MCLK, 1, 0, 0),
{ }
@@ -1438,6 +1444,7 @@ static const struct freq_tbl ftbl_codec_clk[] = {
static struct clk_rcg2 codec_digcodec_clk_src = {
.cmd_rcgr = 0x1c09c,
+ .mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_codec_clk,
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 7983288d9141..1e38efc37180 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -73,6 +73,7 @@ static struct clk_fixed_factor xo = {
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
@@ -88,6 +89,7 @@ static struct clk_alpha_pll gpll0_early = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll0",
@@ -99,6 +101,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_early = {
.offset = 0x1dc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
@@ -114,6 +117,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x1dc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll4",
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 7ddec886fcd3..5d7451209206 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -227,6 +227,7 @@ static struct clk_fixed_factor xo = {
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
@@ -252,6 +253,7 @@ static struct clk_fixed_factor gpll0_early_div = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){ "gpll0_early" },
@@ -262,6 +264,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
@@ -276,6 +279,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_names = (const char *[]){ "gpll4_early" },
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 352394d8fd8c..66a2fa4ec93c 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -267,6 +267,7 @@ static struct pll_vco mmpll_t_vco[] = {
static struct clk_alpha_pll mmpll0_early = {
.offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
@@ -283,6 +284,7 @@ static struct clk_alpha_pll mmpll0_early = {
static struct clk_alpha_pll_postdiv mmpll0 = {
.offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
@@ -295,6 +297,7 @@ static struct clk_alpha_pll_postdiv mmpll0 = {
static struct clk_alpha_pll mmpll1_early = {
.offset = 0x30,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
@@ -311,6 +314,7 @@ static struct clk_alpha_pll mmpll1_early = {
static struct clk_alpha_pll_postdiv mmpll1 = {
.offset = 0x30,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
@@ -323,6 +327,7 @@ static struct clk_alpha_pll_postdiv mmpll1 = {
static struct clk_alpha_pll mmpll2_early = {
.offset = 0x4100,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -335,6 +340,7 @@ static struct clk_alpha_pll mmpll2_early = {
static struct clk_alpha_pll_postdiv mmpll2 = {
.offset = 0x4100,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
@@ -347,6 +353,7 @@ static struct clk_alpha_pll_postdiv mmpll2 = {
static struct clk_alpha_pll mmpll3_early = {
.offset = 0x60,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -359,6 +366,7 @@ static struct clk_alpha_pll mmpll3_early = {
static struct clk_alpha_pll_postdiv mmpll3 = {
.offset = 0x60,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
@@ -371,6 +379,7 @@ static struct clk_alpha_pll_postdiv mmpll3 = {
static struct clk_alpha_pll mmpll4_early = {
.offset = 0x90,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -383,6 +392,7 @@ static struct clk_alpha_pll mmpll4_early = {
static struct clk_alpha_pll_postdiv mmpll4 = {
.offset = 0x90,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
@@ -395,6 +405,7 @@ static struct clk_alpha_pll_postdiv mmpll4 = {
static struct clk_alpha_pll mmpll5_early = {
.offset = 0xc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -407,6 +418,7 @@ static struct clk_alpha_pll mmpll5_early = {
static struct clk_alpha_pll_postdiv mmpll5 = {
.offset = 0xc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5",
@@ -419,6 +431,7 @@ static struct clk_alpha_pll_postdiv mmpll5 = {
static struct clk_alpha_pll mmpll8_early = {
.offset = 0x4130,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -431,6 +444,7 @@ static struct clk_alpha_pll mmpll8_early = {
static struct clk_alpha_pll_postdiv mmpll8 = {
.offset = 0x4130,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll8",
@@ -443,6 +457,7 @@ static struct clk_alpha_pll_postdiv mmpll8 = {
static struct clk_alpha_pll mmpll9_early = {
.offset = 0x4200,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -455,6 +470,7 @@ static struct clk_alpha_pll mmpll9_early = {
static struct clk_alpha_pll_postdiv mmpll9 = {
.offset = 0x4200,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll9",
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index c944cc421e30..858c24d4da8f 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -341,7 +341,7 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
return;
pd->name = np->name;
- pd->flags = GENPD_FLAG_PM_CLK;
+ pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
pd->attach_dev = cpg_mstp_attach_dev;
pd->detach_dev = cpg_mstp_detach_dev;
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index b3767472088a..41e29734126b 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
+ DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index 72f98527473a..f55842917e8d 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -105,6 +105,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e3d03ffea4bc..e3cc72c81311 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -513,7 +513,7 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
genpd = &pd->genpd;
genpd->name = np->name;
- genpd->flags = GENPD_FLAG_PM_CLK;
+ genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = cpg_mssr_attach_dev;
genpd->detach_dev = cpg_mssr_detach_dev;
pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index 229c96daece6..f5be02205ac6 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -131,7 +131,7 @@ struct clk *clk_register_frac(const char *name, const char *parent_name,
struct clk *clk;
if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
- pr_err("Invalid arguments passed");
+ pr_err("Invalid arguments passed\n");
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
index 28262f422562..6ed406d943ba 100644
--- a/drivers/clk/spear/clk-gpt-synth.c
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -120,7 +120,7 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
struct clk *clk;
if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
- pr_err("Invalid arguments passed");
+ pr_err("Invalid arguments passed\n");
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/sprd/Kconfig b/drivers/clk/sprd/Kconfig
new file mode 100644
index 000000000000..87892471eb96
--- /dev/null
+++ b/drivers/clk/sprd/Kconfig
@@ -0,0 +1,14 @@
+config SPRD_COMMON_CLK
+ tristate "Clock support for Spreadtrum SoCs"
+ depends on ARCH_SPRD || COMPILE_TEST
+ default ARCH_SPRD
+
+if SPRD_COMMON_CLK
+
+# SoC Drivers
+
+config SPRD_SC9860_CLK
+ tristate "Support for the Spreadtrum SC9860 clocks"
+ depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
+ default ARM64 && ARCH_SPRD
+endif
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
new file mode 100644
index 000000000000..b0d81e541ebd
--- /dev/null
+++ b/drivers/clk/sprd/Makefile
@@ -0,0 +1,11 @@
+obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o
+
+clk-sprd-y += common.o
+clk-sprd-y += gate.o
+clk-sprd-y += mux.o
+clk-sprd-y += div.o
+clk-sprd-y += composite.o
+clk-sprd-y += pll.o
+
+## SoC support
+obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o
diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c
new file mode 100644
index 000000000000..e038b0447206
--- /dev/null
+++ b/drivers/clk/sprd/common.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum clock infrastructure
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+#include "common.h"
+
+static const struct regmap_config sprdclk_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xffff,
+ .fast_io = true,
+};
+
+static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc,
+ struct regmap *regmap)
+{
+ int i;
+ struct sprd_clk_common *cclk;
+
+ for (i = 0; i < desc->num_clk_clks; i++) {
+ cclk = desc->clk_clks[i];
+ if (!cclk)
+ continue;
+
+ cclk->regmap = regmap;
+ }
+}
+
+int sprd_clk_regmap_init(struct platform_device *pdev,
+ const struct sprd_clk_desc *desc)
+{
+ void __iomem *base;
+ struct device_node *node = pdev->dev.of_node;
+ struct regmap *regmap;
+
+ if (of_find_property(node, "sprd,syscon", NULL)) {
+ regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");
+ if (IS_ERR_OR_NULL(regmap)) {
+ pr_err("%s: failed to get syscon regmap\n", __func__);
+ return PTR_ERR(regmap);
+ }
+ } else {
+ base = of_iomap(node, 0);
+ regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &sprdclk_regmap_config);
+ if (IS_ERR_OR_NULL(regmap)) {
+ pr_err("failed to init regmap\n");
+ return PTR_ERR(regmap);
+ }
+ }
+
+ sprd_clk_set_regmap(desc, regmap);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(sprd_clk_regmap_init);
+
+int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)
+{
+ int i, ret;
+ struct clk_hw *hw;
+
+ for (i = 0; i < clkhw->num; i++) {
+
+ hw = clkhw->hws[i];
+
+ if (!hw)
+ continue;
+
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret) {
+ dev_err(dev, "Couldn't register clock %d - %s\n",
+ i, hw->init->name);
+ return ret;
+ }
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw);
+ if (ret)
+ dev_err(dev, "Failed to add clock provider\n");
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sprd_clk_probe);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sprd/common.h b/drivers/clk/sprd/common.h
new file mode 100644
index 000000000000..abd9ff5ef448
--- /dev/null
+++ b/drivers/clk/sprd/common.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum clock infrastructure
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_CLK_COMMON_H_
+#define _SPRD_CLK_COMMON_H_
+
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+struct device_node;
+
+struct sprd_clk_common {
+ struct regmap *regmap;
+ u32 reg;
+ struct clk_hw hw;
+};
+
+struct sprd_clk_desc {
+ struct sprd_clk_common **clk_clks;
+ unsigned long num_clk_clks;
+ struct clk_hw_onecell_data *hw_clks;
+};
+
+static inline struct sprd_clk_common *
+ hw_to_sprd_clk_common(const struct clk_hw *hw)
+{
+ return container_of(hw, struct sprd_clk_common, hw);
+}
+int sprd_clk_regmap_init(struct platform_device *pdev,
+ const struct sprd_clk_desc *desc);
+int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw);
+
+#endif /* _SPRD_CLK_COMMON_H_ */
diff --git a/drivers/clk/sprd/composite.c b/drivers/clk/sprd/composite.c
new file mode 100644
index 000000000000..ebb644820b1e
--- /dev/null
+++ b/drivers/clk/sprd/composite.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum composite clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/clk-provider.h>
+
+#include "composite.h"
+
+static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_round_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
+}
+
+static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_set_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static u8 sprd_comp_get_parent(struct clk_hw *hw)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_get_parent(&cc->common, &cc->mux);
+}
+
+static int sprd_comp_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index);
+}
+
+const struct clk_ops sprd_comp_ops = {
+ .get_parent = sprd_comp_get_parent,
+ .set_parent = sprd_comp_set_parent,
+
+ .round_rate = sprd_comp_round_rate,
+ .recalc_rate = sprd_comp_recalc_rate,
+ .set_rate = sprd_comp_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_comp_ops);
diff --git a/drivers/clk/sprd/composite.h b/drivers/clk/sprd/composite.h
new file mode 100644
index 000000000000..0984e9e252dc
--- /dev/null
+++ b/drivers/clk/sprd/composite.h
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum composite clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_COMPOSITE_H_
+#define _SPRD_COMPOSITE_H_
+
+#include "common.h"
+#include "mux.h"
+#include "div.h"
+
+struct sprd_comp {
+ struct sprd_mux_ssel mux;
+ struct sprd_div_internal div;
+ struct sprd_clk_common common;
+};
+
+#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
+ _mshift, _mwidth, _dshift, _dwidth, _flags) \
+ struct sprd_comp _struct = { \
+ .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
+ .div = _SPRD_DIV_CLK(_dshift, _dwidth), \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parent, \
+ &sprd_comp_ops, \
+ _flags), \
+ } \
+ }
+
+#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
+ _mwidth, _dshift, _dwidth, _flags) \
+ SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
+ NULL, _mshift, _mwidth, \
+ _dshift, _dwidth, _flags)
+
+static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_comp, common);
+}
+
+extern const struct clk_ops sprd_comp_ops;
+
+#endif /* _SPRD_COMPOSITE_H_ */
diff --git a/drivers/clk/sprd/div.c b/drivers/clk/sprd/div.c
new file mode 100644
index 000000000000..7621a1d1ab9c
--- /dev/null
+++ b/drivers/clk/sprd/div.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum divider clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/clk-provider.h>
+
+#include "div.h"
+
+long sprd_div_helper_round_rate(struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return divider_round_rate(&common->hw, rate, parent_rate,
+ NULL, div->width, 0);
+}
+EXPORT_SYMBOL_GPL(sprd_div_helper_round_rate);
+
+static long sprd_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sprd_div *cd = hw_to_sprd_div(hw);
+
+ return sprd_div_helper_round_rate(&cd->common, &cd->div,
+ rate, parent_rate);
+}
+
+unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long parent_rate)
+{
+ unsigned long val;
+ unsigned int reg;
+
+ regmap_read(common->regmap, common->reg, &reg);
+ val = reg >> div->shift;
+ val &= (1 << div->width) - 1;
+
+ return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0,
+ div->width);
+}
+EXPORT_SYMBOL_GPL(sprd_div_helper_recalc_rate);
+
+static unsigned long sprd_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_div *cd = hw_to_sprd_div(hw);
+
+ return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
+}
+
+int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ unsigned long val;
+ unsigned int reg;
+
+ val = divider_get_val(rate, parent_rate, NULL,
+ div->width, 0);
+
+ regmap_read(common->regmap, common->reg, &reg);
+ reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
+
+ regmap_write(common->regmap, common->reg,
+ reg | (val << div->shift));
+
+ return 0;
+
+}
+EXPORT_SYMBOL_GPL(sprd_div_helper_set_rate);
+
+static int sprd_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_div *cd = hw_to_sprd_div(hw);
+
+ return sprd_div_helper_set_rate(&cd->common, &cd->div,
+ rate, parent_rate);
+}
+
+const struct clk_ops sprd_div_ops = {
+ .recalc_rate = sprd_div_recalc_rate,
+ .round_rate = sprd_div_round_rate,
+ .set_rate = sprd_div_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_div_ops);
diff --git a/drivers/clk/sprd/div.h b/drivers/clk/sprd/div.h
new file mode 100644
index 000000000000..b3033d24d431
--- /dev/null
+++ b/drivers/clk/sprd/div.h
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum divider clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_DIV_H_
+#define _SPRD_DIV_H_
+
+#include "common.h"
+
+/**
+ * struct sprd_div_internal - Internal divider description
+ * @shift: Bit offset of the divider in its register
+ * @width: Width of the divider field in its register
+ *
+ * That structure represents a single divider, and is meant to be
+ * embedded in other structures representing the various clock
+ * classes.
+ */
+struct sprd_div_internal {
+ u8 shift;
+ u8 width;
+};
+
+#define _SPRD_DIV_CLK(_shift, _width) \
+ { \
+ .shift = _shift, \
+ .width = _width, \
+ }
+
+struct sprd_div {
+ struct sprd_div_internal div;
+ struct sprd_clk_common common;
+};
+
+#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
+ _shift, _width, _flags) \
+ struct sprd_div _struct = { \
+ .div = _SPRD_DIV_CLK(_shift, _width), \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ &sprd_div_ops, \
+ _flags), \
+ } \
+ }
+
+static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_div, common);
+}
+
+long sprd_div_helper_round_rate(struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long rate,
+ unsigned long *parent_rate);
+
+unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long parent_rate);
+
+int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
+ const struct sprd_div_internal *div,
+ unsigned long rate,
+ unsigned long parent_rate);
+
+extern const struct clk_ops sprd_div_ops;
+
+#endif /* _SPRD_DIV_H_ */
diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c
new file mode 100644
index 000000000000..f59d1936b412
--- /dev/null
+++ b/drivers/clk/sprd/gate.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum gate clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "gate.h"
+
+static void clk_gate_toggle(const struct sprd_gate *sg, bool en)
+{
+ const struct sprd_clk_common *common = &sg->common;
+ unsigned int reg;
+ bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? true : false;
+
+ set ^= en;
+
+ regmap_read(common->regmap, common->reg, &reg);
+
+ if (set)
+ reg |= sg->enable_mask;
+ else
+ reg &= ~sg->enable_mask;
+
+ regmap_write(common->regmap, common->reg, reg);
+}
+
+static void clk_sc_gate_toggle(const struct sprd_gate *sg, bool en)
+{
+ const struct sprd_clk_common *common = &sg->common;
+ bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+ unsigned int offset;
+
+ set ^= en;
+
+ /*
+ * Each set/clear gate clock has three registers:
+ * common->reg - base register
+ * common->reg + offset - set register
+ * common->reg + 2 * offset - clear register
+ */
+ offset = set ? sg->sc_offset : sg->sc_offset * 2;
+
+ regmap_write(common->regmap, common->reg + offset,
+ sg->enable_mask);
+}
+
+static void sprd_gate_disable(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+
+ clk_gate_toggle(sg, false);
+}
+
+static int sprd_gate_enable(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+
+ clk_gate_toggle(sg, true);
+
+ return 0;
+}
+
+static void sprd_sc_gate_disable(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+
+ clk_sc_gate_toggle(sg, false);
+}
+
+static int sprd_sc_gate_enable(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+
+ clk_sc_gate_toggle(sg, true);
+
+ return 0;
+}
+static int sprd_gate_is_enabled(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+ struct sprd_clk_common *common = &sg->common;
+ unsigned int reg;
+
+ regmap_read(common->regmap, common->reg, &reg);
+
+ if (sg->flags & CLK_GATE_SET_TO_DISABLE)
+ reg ^= sg->enable_mask;
+
+ reg &= sg->enable_mask;
+
+ return reg ? 1 : 0;
+}
+
+const struct clk_ops sprd_gate_ops = {
+ .disable = sprd_gate_disable,
+ .enable = sprd_gate_enable,
+ .is_enabled = sprd_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(sprd_gate_ops);
+
+const struct clk_ops sprd_sc_gate_ops = {
+ .disable = sprd_sc_gate_disable,
+ .enable = sprd_sc_gate_enable,
+ .is_enabled = sprd_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
+
diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
new file mode 100644
index 000000000000..2e582c68a08b
--- /dev/null
+++ b/drivers/clk/sprd/gate.h
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum gate clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_GATE_H_
+#define _SPRD_GATE_H_
+
+#include "common.h"
+
+struct sprd_gate {
+ u32 enable_mask;
+ u16 flags;
+ u16 sc_offset;
+
+ struct sprd_clk_common common;
+};
+
+#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
+ _enable_mask, _flags, _gate_flags, _ops) \
+ struct sprd_gate _struct = { \
+ .enable_mask = _enable_mask, \
+ .sc_offset = _sc_offset, \
+ .flags = _gate_flags, \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ _ops, \
+ _flags), \
+ } \
+ }
+
+#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
+ _enable_mask, _flags, _gate_flags) \
+ SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
+ _enable_mask, _flags, _gate_flags, \
+ &sprd_gate_ops)
+
+#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
+ _enable_mask, _flags, _gate_flags) \
+ SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
+ _enable_mask, _flags, _gate_flags, \
+ &sprd_sc_gate_ops)
+
+static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_gate, common);
+}
+
+extern const struct clk_ops sprd_gate_ops;
+extern const struct clk_ops sprd_sc_gate_ops;
+
+#endif /* _SPRD_GATE_H_ */
diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c
new file mode 100644
index 000000000000..624041b60358
--- /dev/null
+++ b/drivers/clk/sprd/mux.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum multiplexer clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "mux.h"
+
+u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
+ const struct sprd_mux_ssel *mux)
+{
+ unsigned int reg;
+ u8 parent;
+ int num_parents;
+ int i;
+
+ regmap_read(common->regmap, common->reg, &reg);
+ parent = reg >> mux->shift;
+ parent &= (1 << mux->width) - 1;
+
+ if (!mux->table)
+ return parent;
+
+ num_parents = clk_hw_get_num_parents(&common->hw);
+
+ for (i = 0; i < num_parents - 1; i++)
+ if (parent >= mux->table[i] && parent < mux->table[i + 1])
+ return i;
+
+ return num_parents - 1;
+}
+EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);
+
+static u8 sprd_mux_get_parent(struct clk_hw *hw)
+{
+ struct sprd_mux *cm = hw_to_sprd_mux(hw);
+
+ return sprd_mux_helper_get_parent(&cm->common, &cm->mux);
+}
+
+int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
+ const struct sprd_mux_ssel *mux,
+ u8 index)
+{
+ unsigned int reg;
+
+ if (mux->table)
+ index = mux->table[index];
+
+ regmap_read(common->regmap, common->reg, &reg);
+ reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);
+ regmap_write(common->regmap, common->reg,
+ reg | (index << mux->shift));
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);
+
+static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sprd_mux *cm = hw_to_sprd_mux(hw);
+
+ return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);
+}
+
+const struct clk_ops sprd_mux_ops = {
+ .get_parent = sprd_mux_get_parent,
+ .set_parent = sprd_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_mux_ops);
diff --git a/drivers/clk/sprd/mux.h b/drivers/clk/sprd/mux.h
new file mode 100644
index 000000000000..548cfa0f145c
--- /dev/null
+++ b/drivers/clk/sprd/mux.h
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum multiplexer clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_MUX_H_
+#define _SPRD_MUX_H_
+
+#include "common.h"
+
+/**
+ * struct sprd_mux_ssel - Mux clock's source select bits in its register
+ * @shift: Bit offset of the divider in its register
+ * @width: Width of the divider field in its register
+ * @table: For some mux clocks, not all sources are used on some special
+ * chips, this matches the value of mux clock's register and the
+ * sources which are used for this mux clock
+ */
+struct sprd_mux_ssel {
+ u8 shift;
+ u8 width;
+ const u8 *table;
+};
+
+struct sprd_mux {
+ struct sprd_mux_ssel mux;
+ struct sprd_clk_common common;
+};
+
+#define _SPRD_MUX_CLK(_shift, _width, _table) \
+ { \
+ .shift = _shift, \
+ .width = _width, \
+ .table = _table, \
+ }
+
+#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
+ _reg, _shift, _width, \
+ _flags) \
+ struct sprd_mux _struct = { \
+ .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parents, \
+ &sprd_mux_ops, \
+ _flags), \
+ } \
+ }
+
+#define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
+ _shift, _width, _flags) \
+ SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
+ _reg, _shift, _width, _flags)
+
+static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_mux, common);
+}
+
+extern const struct clk_ops sprd_mux_ops;
+
+u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
+ const struct sprd_mux_ssel *mux);
+int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
+ const struct sprd_mux_ssel *mux,
+ u8 index);
+
+#endif /* _SPRD_MUX_H_ */
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
new file mode 100644
index 000000000000..36b4402bf09e
--- /dev/null
+++ b/drivers/clk/sprd/pll.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum pll clock driver
+//
+// Copyright (C) 2015~2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "pll.h"
+
+#define CLK_PLL_1M 1000000
+#define CLK_PLL_10M (CLK_PLL_1M * 10)
+
+#define pindex(pll, member) \
+ (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
+
+#define pshift(pll, member) \
+ (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
+
+#define pwidth(pll, member) \
+ pll->factors[member].width
+
+#define pmask(pll, member) \
+ ((pwidth(pll, member)) ? \
+ GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
+ pshift(pll, member)) : 0)
+
+#define pinternal(pll, cfg, member) \
+ (cfg[pindex(pll, member)] & pmask(pll, member))
+
+#define pinternal_val(pll, cfg, member) \
+ (pinternal(pll, cfg, member) >> pshift(pll, member))
+
+static inline unsigned int
+sprd_pll_read(const struct sprd_pll *pll, u8 index)
+{
+ const struct sprd_clk_common *common = &pll->common;
+ unsigned int val = 0;
+
+ if (WARN_ON(index >= pll->regs_num))
+ return 0;
+
+ regmap_read(common->regmap, common->reg + index * 4, &val);
+
+ return val;
+}
+
+static inline void
+sprd_pll_write(const struct sprd_pll *pll, u8 index,
+ u32 msk, u32 val)
+{
+ const struct sprd_clk_common *common = &pll->common;
+ unsigned int offset, reg;
+ int ret = 0;
+
+ if (WARN_ON(index >= pll->regs_num))
+ return;
+
+ offset = common->reg + index * 4;
+ ret = regmap_read(common->regmap, offset, &reg);
+ if (!ret)
+ regmap_write(common->regmap, offset, (reg & ~msk) | val);
+}
+
+static unsigned long pll_get_refin(const struct sprd_pll *pll)
+{
+ u32 shift, mask, index, refin_id = 3;
+ const unsigned long refin[4] = { 2, 4, 13, 26 };
+
+ if (pwidth(pll, PLL_REFIN)) {
+ index = pindex(pll, PLL_REFIN);
+ shift = pshift(pll, PLL_REFIN);
+ mask = pmask(pll, PLL_REFIN);
+ refin_id = (sprd_pll_read(pll, index) & mask) >> shift;
+ if (refin_id > 3)
+ refin_id = 3;
+ }
+
+ return refin[refin_id];
+}
+
+static u32 pll_get_ibias(u64 rate, const u64 *table)
+{
+ u32 i, num = table[0];
+
+ for (i = 1; i < num + 1; i++)
+ if (rate <= table[i])
+ break;
+
+ return (i == num + 1) ? num : i;
+}
+
+static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
+ unsigned long parent_rate)
+{
+ u32 *cfg;
+ u32 i, mask, regs_num = pll->regs_num;
+ unsigned long rate, nint, kint = 0;
+ u64 refin;
+ u16 k1, k2;
+
+ cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+
+ for (i = 0; i < regs_num; i++)
+ cfg[i] = sprd_pll_read(pll, i);
+
+ refin = pll_get_refin(pll);
+
+ if (pinternal(pll, cfg, PLL_PREDIV))
+ refin = refin * 2;
+
+ if (pwidth(pll, PLL_POSTDIV) &&
+ ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) ||
+ (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV))))
+ refin = refin / 2;
+
+ if (!pinternal(pll, cfg, PLL_DIV_S)) {
+ rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M;
+ } else {
+ nint = pinternal_val(pll, cfg, PLL_NINT);
+ if (pinternal(pll, cfg, PLL_SDM_EN))
+ kint = pinternal_val(pll, cfg, PLL_KINT);
+
+ mask = pmask(pll, PLL_KINT);
+
+ k1 = pll->k1;
+ k2 = pll->k2;
+ rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1,
+ ((mask >> __ffs(mask)) + 1)) *
+ k2 + refin * nint * CLK_PLL_1M;
+ }
+
+ return rate;
+}
+
+#define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \
+ (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT))
+
+static int _sprd_pll_set_rate(const struct sprd_pll *pll,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct reg_cfg *cfg;
+ int ret = 0;
+ u32 mask, shift, width, ibias_val, index;
+ u32 regs_num = pll->regs_num, i = 0;
+ unsigned long kint, nint;
+ u64 tmp, refin, fvco = rate;
+
+ cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+
+ refin = pll_get_refin(pll);
+
+ mask = pmask(pll, PLL_PREDIV);
+ index = pindex(pll, PLL_PREDIV);
+ width = pwidth(pll, PLL_PREDIV);
+ if (width && (sprd_pll_read(pll, index) & mask))
+ refin = refin * 2;
+
+ mask = pmask(pll, PLL_POSTDIV);
+ index = pindex(pll, PLL_POSTDIV);
+ width = pwidth(pll, PLL_POSTDIV);
+ cfg[index].msk = mask;
+ if (width && ((pll->fflag == 1 && fvco <= pll->fvco) ||
+ (pll->fflag == 0 && fvco > pll->fvco)))
+ cfg[index].val |= mask;
+
+ if (width && fvco <= pll->fvco)
+ fvco = fvco * 2;
+
+ mask = pmask(pll, PLL_DIV_S);
+ index = pindex(pll, PLL_DIV_S);
+ cfg[index].val |= mask;
+ cfg[index].msk |= mask;
+
+ mask = pmask(pll, PLL_SDM_EN);
+ index = pindex(pll, PLL_SDM_EN);
+ cfg[index].val |= mask;
+ cfg[index].msk |= mask;
+
+ nint = do_div(fvco, refin * CLK_PLL_1M);
+ mask = pmask(pll, PLL_NINT);
+ index = pindex(pll, PLL_NINT);
+ shift = pshift(pll, PLL_NINT);
+ cfg[index].val |= (nint << shift) & mask;
+ cfg[index].msk |= mask;
+
+ mask = pmask(pll, PLL_KINT);
+ index = pindex(pll, PLL_KINT);
+ width = pwidth(pll, PLL_KINT);
+ shift = pshift(pll, PLL_KINT);
+ tmp = fvco - refin * nint * CLK_PLL_1M;
+ tmp = do_div(tmp, 10000) * ((mask >> shift) + 1);
+ kint = DIV_ROUND_CLOSEST_ULL(tmp, refin * 100);
+ cfg[index].val |= (kint << shift) & mask;
+ cfg[index].msk |= mask;
+
+ ibias_val = pll_get_ibias(fvco, pll->itable);
+
+ mask = pmask(pll, PLL_IBIAS);
+ index = pindex(pll, PLL_IBIAS);
+ shift = pshift(pll, PLL_IBIAS);
+ cfg[index].val |= ibias_val << shift & mask;
+ cfg[index].msk |= mask;
+
+ for (i = 0; i < regs_num; i++) {
+ if (cfg[i].msk) {
+ sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val);
+ ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk,
+ cfg[i].val);
+ }
+ }
+
+ if (!ret)
+ udelay(pll->udelay);
+
+ return ret;
+}
+
+static unsigned long sprd_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ return _sprd_pll_recalc_rate(pll, parent_rate);
+}
+
+static int sprd_pll_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ return _sprd_pll_set_rate(pll, rate, parent_rate);
+}
+
+static int sprd_pll_clk_prepare(struct clk_hw *hw)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ udelay(pll->udelay);
+
+ return 0;
+}
+
+static long sprd_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate;
+}
+
+const struct clk_ops sprd_pll_ops = {
+ .prepare = sprd_pll_clk_prepare,
+ .recalc_rate = sprd_pll_recalc_rate,
+ .round_rate = sprd_pll_round_rate,
+ .set_rate = sprd_pll_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_pll_ops);
diff --git a/drivers/clk/sprd/pll.h b/drivers/clk/sprd/pll.h
new file mode 100644
index 000000000000..514175621099
--- /dev/null
+++ b/drivers/clk/sprd/pll.h
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreadtrum pll clock driver
+//
+// Copyright (C) 2015~2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#ifndef _SPRD_PLL_H_
+#define _SPRD_PLL_H_
+
+#include "common.h"
+
+struct reg_cfg {
+ u32 val;
+ u32 msk;
+};
+
+struct clk_bit_field {
+ u8 shift;
+ u8 width;
+};
+
+enum {
+ PLL_LOCK_DONE,
+ PLL_DIV_S,
+ PLL_MOD_EN,
+ PLL_SDM_EN,
+ PLL_REFIN,
+ PLL_IBIAS,
+ PLL_N,
+ PLL_NINT,
+ PLL_KINT,
+ PLL_PREDIV,
+ PLL_POSTDIV,
+
+ PLL_FACT_MAX
+};
+
+/*
+ * struct sprd_pll - definition of adjustable pll clock
+ *
+ * @reg: registers used to set the configuration of pll clock,
+ * reg[0] shows how many registers this pll clock uses.
+ * @itable: pll ibias table, itable[0] means how many items this
+ * table includes
+ * @udelay delay time after setting rate
+ * @factors used to calculate the pll clock rate
+ * @fvco: fvco threshold rate
+ * @fflag: fvco flag
+ */
+struct sprd_pll {
+ u32 regs_num;
+ const u64 *itable;
+ const struct clk_bit_field *factors;
+ u16 udelay;
+ u16 k1;
+ u16 k2;
+ u16 fflag;
+ u64 fvco;
+
+ struct sprd_clk_common common;
+};
+
+#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2, _fflag, _fvco) \
+ struct sprd_pll _struct = { \
+ .regs_num = _regs_num, \
+ .itable = _itable, \
+ .factors = _factors, \
+ .udelay = _udelay, \
+ .k1 = _k1, \
+ .k2 = _k2, \
+ .fflag = _fflag, \
+ .fvco = _fvco, \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ &sprd_pll_ops, \
+ 0), \
+ }, \
+ }
+
+#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2) \
+ SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2, 0, 0)
+
+#define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, _udelay) \
+ SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, 1000, 1000, 0, 0)
+
+static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_pll, common);
+}
+
+extern const struct clk_ops sprd_pll_ops;
+
+#endif /* _SPRD_PLL_H_ */
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
new file mode 100644
index 000000000000..ed5c027df0f4
--- /dev/null
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -0,0 +1,1974 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Spreatrum SC9860 clock driver
+//
+// Copyright (C) 2017 Spreadtrum, Inc.
+// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/sprd,sc9860-clk.h>
+
+#include "common.h"
+#include "composite.h"
+#include "div.h"
+#include "gate.h"
+#include "mux.h"
+#include "pll.h"
+
+static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
+ 6, 1, 0);
+static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
+ 13, 1, 0);
+static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
+ 26, 1, 0);
+static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
+ 104, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
+ 1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
+ 1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
+ 4, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
+ 25, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
+ 50, 1, 0);
+static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
+ 10, 1, 0);
+static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
+ 32, 1, 0);
+
+static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c,
+ 0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
+
+static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
+ /* address base is 0x402b0000 */
+ &mpll0_gate.common,
+ &mpll1_gate.common,
+ &dpll0_gate.common,
+ &dpll1_gate.common,
+ &ltepll0_gate.common,
+ &twpll_gate.common,
+ &ltepll1_gate.common,
+ &rpll0_gate.common,
+ &rpll1_gate.common,
+ &cppll_gate.common,
+ &gpll_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {
+ .hws = {
+ [CLK_FAC_4M] = &fac_4m.hw,
+ [CLK_FAC_2M] = &fac_2m.hw,
+ [CLK_FAC_1M] = &fac_1m.hw,
+ [CLK_FAC_250K] = &fac_250k.hw,
+ [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw,
+ [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw,
+ [CLK_FAC_RCO25M] = &fac_rco_25m.hw,
+ [CLK_FAC_RCO4M] = &fac_rco_4m.hw,
+ [CLK_FAC_RCO2M] = &fac_rco_2m.hw,
+ [CLK_FAC_3K2] = &fac_3k2.hw,
+ [CLK_FAC_1K] = &fac_1k.hw,
+ [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,
+ [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,
+ [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,
+ [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,
+ [CLK_LTEPLL0_GATE] = &ltepll0_gate.common.hw,
+ [CLK_TWPLL_GATE] = &twpll_gate.common.hw,
+ [CLK_LTEPLL1_GATE] = &ltepll1_gate.common.hw,
+ [CLK_RPLL0_GATE] = &rpll0_gate.common.hw,
+ [CLK_RPLL1_GATE] = &rpll1_gate.common.hw,
+ [CLK_CPPLL_GATE] = &cppll_gate.common.hw,
+ [CLK_GPLL_GATE] = &gpll_gate.common.hw,
+ },
+ .num = CLK_PMU_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_pmu_gate_desc = {
+ .clk_clks = sc9860_pmu_gate_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks),
+ .hw_clks = &sc9860_pmu_gate_hws,
+};
+
+/* GPLL/LPLL/DPLL/RPLL/CPLL */
+static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000};
+
+/* TWPLL/MPLL0/MPLL1 */
+static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
+
+static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = {
+ { .shift = 20, .width = 1 }, /* lock_done */
+ { .shift = 19, .width = 1 }, /* div_s */
+ { .shift = 18, .width = 1 }, /* mod_en */
+ { .shift = 17, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 11, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 56, .width = 1 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24,
+ 2, itable2, f_mpll0, 200,
+ 1000, 1000, 1, 1300000000);
+
+static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = {
+ { .shift = 20, .width = 1 }, /* lock_done */
+ { .shift = 19, .width = 1 }, /* div_s */
+ { .shift = 18, .width = 1 }, /* mod_en */
+ { .shift = 17, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 11, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 56, .width = 1 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c,
+ 2, itable2, f_mpll1, 200);
+
+static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = {
+ { .shift = 16, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
+ 2, itable1, f_dpll, 200);
+
+static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
+ 2, itable1, f_dpll, 200);
+
+static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = {
+ { .shift = 0, .width = 1 }, /* lock_done */
+ { .shift = 3, .width = 1 }, /* div_s */
+ { .shift = 80, .width = 1 }, /* mod_en */
+ { .shift = 81, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 14, .width = 2 }, /* ibias */
+ { .shift = 16, .width = 7 }, /* n */
+ { .shift = 4, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44,
+ 3, itable1, f_rpll, 200);
+
+static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50,
+ 3, itable1, f_rpll, 200);
+
+static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {
+ { .shift = 21, .width = 1 }, /* lock_done */
+ { .shift = 20, .width = 1 }, /* div_s */
+ { .shift = 19, .width = 1 }, /* mod_en */
+ { .shift = 18, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 13, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c,
+ 2, itable2, f_twpll, 200);
+
+static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = {
+ { .shift = 31, .width = 1 }, /* lock_done */
+ { .shift = 27, .width = 1 }, /* div_s */
+ { .shift = 26, .width = 1 }, /* mod_en */
+ { .shift = 25, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 20, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate",
+ 0x64, 2, itable1,
+ f_ltepll, 200);
+static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate",
+ 0x6c, 2, itable1,
+ f_ltepll, 200);
+
+static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {
+ { .shift = 18, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 17, .width = 1 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
+ 2, itable1, f_gpll, 200,
+ 1000, 1000, 1, 600000000);
+
+static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = {
+ { .shift = 17, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4,
+ 2, itable1, f_cppll, 200);
+
+static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
+static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0);
+static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0);
+static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0);
+static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0);
+static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0);
+static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0);
+static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0);
+static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0);
+static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0);
+static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0);
+static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0);
+static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0);
+static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0);
+static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0);
+static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0);
+static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0);
+static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0);
+static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0);
+static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0);
+static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0);
+static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0);
+static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
+static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
+static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0);
+static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0);
+static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0);
+
+static struct sprd_clk_common *sc9860_pll_clks[] = {
+ /* address base is 0x40400000 */
+ &mpll0_clk.common,
+ &mpll1_clk.common,
+ &dpll0_clk.common,
+ &dpll1_clk.common,
+ &rpll0_clk.common,
+ &rpll1_clk.common,
+ &twpll_clk.common,
+ &ltepll0_clk.common,
+ &ltepll1_clk.common,
+ &gpll_clk.common,
+ &cppll_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_pll_hws = {
+ .hws = {
+ [CLK_MPLL0] = &mpll0_clk.common.hw,
+ [CLK_MPLL1] = &mpll1_clk.common.hw,
+ [CLK_DPLL0] = &dpll0_clk.common.hw,
+ [CLK_DPLL1] = &dpll1_clk.common.hw,
+ [CLK_RPLL0] = &rpll0_clk.common.hw,
+ [CLK_RPLL1] = &rpll1_clk.common.hw,
+ [CLK_TWPLL] = &twpll_clk.common.hw,
+ [CLK_LTEPLL0] = &ltepll0_clk.common.hw,
+ [CLK_LTEPLL1] = &ltepll1_clk.common.hw,
+ [CLK_GPLL] = &gpll_clk.common.hw,
+ [CLK_CPPLL] = &cppll_clk.common.hw,
+ [CLK_GPLL_42M5] = &gpll_42m5.hw,
+ [CLK_TWPLL_768M] = &twpll_768m.hw,
+ [CLK_TWPLL_384M] = &twpll_384m.hw,
+ [CLK_TWPLL_192M] = &twpll_192m.hw,
+ [CLK_TWPLL_96M] = &twpll_96m.hw,
+ [CLK_TWPLL_48M] = &twpll_48m.hw,
+ [CLK_TWPLL_24M] = &twpll_24m.hw,
+ [CLK_TWPLL_12M] = &twpll_12m.hw,
+ [CLK_TWPLL_512M] = &twpll_512m.hw,
+ [CLK_TWPLL_256M] = &twpll_256m.hw,
+ [CLK_TWPLL_128M] = &twpll_128m.hw,
+ [CLK_TWPLL_64M] = &twpll_64m.hw,
+ [CLK_TWPLL_307M2] = &twpll_307m2.hw,
+ [CLK_TWPLL_153M6] = &twpll_153m6.hw,
+ [CLK_TWPLL_76M8] = &twpll_76m8.hw,
+ [CLK_TWPLL_51M2] = &twpll_51m2.hw,
+ [CLK_TWPLL_38M4] = &twpll_38m4.hw,
+ [CLK_TWPLL_19M2] = &twpll_19m2.hw,
+ [CLK_L0_614M4] = &l0_614m4.hw,
+ [CLK_L0_409M6] = &l0_409m6.hw,
+ [CLK_L0_38M] = &l0_38m.hw,
+ [CLK_L1_38M] = &l1_38m.hw,
+ [CLK_RPLL0_192M] = &rpll0_192m.hw,
+ [CLK_RPLL0_96M] = &rpll0_96m.hw,
+ [CLK_RPLL0_48M] = &rpll0_48m.hw,
+ [CLK_RPLL1_468M] = &rpll1_468m.hw,
+ [CLK_RPLL1_192M] = &rpll1_192m.hw,
+ [CLK_RPLL1_96M] = &rpll1_96m.hw,
+ [CLK_RPLL1_64M] = &rpll1_64m.hw,
+ [CLK_RPLL1_48M] = &rpll1_48m.hw,
+ [CLK_DPLL0_50M] = &dpll0_50m.hw,
+ [CLK_DPLL1_50M] = &dpll1_50m.hw,
+ [CLK_CPPLL_50M] = &cppll_50m.hw,
+ [CLK_M0_39M] = &m0_39m.hw,
+ [CLK_M1_63M] = &m1_63m.hw,
+ },
+ .num = CLK_PLL_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_pll_desc = {
+ .clk_clks = sc9860_pll_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks),
+ .hw_clks = &sc9860_pll_hws,
+};
+
+#define SC9860_MUX_FLAG \
+ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
+
+static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m",
+ "twpll-96m", "twpll-128m" };
+static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents,
+ 0x20, 0, 1, SC9860_MUX_FLAG);
+
+static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" };
+static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3,
+ 0x2c, 0, 1, SC9860_MUX_FLAG);
+
+static const char * const uart_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-51m2", "twpll-96m" };
+static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
+ 0, 2, 8, 3, 0);
+
+static const char * const i2c_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-51m2", "twpll-153m6" };
+static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58,
+ 0, 2, 8, 3, 0);
+
+static const char * const spi_parents[] = { "ext-26m", "twpll-128m",
+ "twpll-153m6", "twpll-192m" };
+static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
+ 0, 2, 8, 3, 0);
+
+static const char * const iis_parents[] = { "ext-26m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78,
+ 0, 2, 8, 6, 0);
+
+static struct sprd_clk_common *sc9860_ap_clks[] = {
+ /* address base is 0x20000000 */
+ &ap_apb.common,
+ &ap_usb3.common,
+ &uart0_clk.common,
+ &uart1_clk.common,
+ &uart2_clk.common,
+ &uart3_clk.common,
+ &uart4_clk.common,
+ &i2c0_clk.common,
+ &i2c1_clk.common,
+ &i2c2_clk.common,
+ &i2c3_clk.common,
+ &i2c4_clk.common,
+ &i2c5_clk.common,
+ &spi0_clk.common,
+ &spi1_clk.common,
+ &spi2_clk.common,
+ &spi3_clk.common,
+ &iis0_clk.common,
+ &iis1_clk.common,
+ &iis2_clk.common,
+ &iis3_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_ap_clk_hws = {
+ .hws = {
+ [CLK_AP_APB] = &ap_apb.common.hw,
+ [CLK_AP_USB3] = &ap_usb3.common.hw,
+ [CLK_UART0] = &uart0_clk.common.hw,
+ [CLK_UART1] = &uart1_clk.common.hw,
+ [CLK_UART2] = &uart2_clk.common.hw,
+ [CLK_UART3] = &uart3_clk.common.hw,
+ [CLK_UART4] = &uart4_clk.common.hw,
+ [CLK_I2C0] = &i2c0_clk.common.hw,
+ [CLK_I2C1] = &i2c1_clk.common.hw,
+ [CLK_I2C2] = &i2c2_clk.common.hw,
+ [CLK_I2C3] = &i2c3_clk.common.hw,
+ [CLK_I2C4] = &i2c4_clk.common.hw,
+ [CLK_I2C5] = &i2c5_clk.common.hw,
+ [CLK_SPI0] = &spi0_clk.common.hw,
+ [CLK_SPI1] = &spi1_clk.common.hw,
+ [CLK_SPI2] = &spi2_clk.common.hw,
+ [CLK_SPI3] = &spi3_clk.common.hw,
+ [CLK_IIS0] = &iis0_clk.common.hw,
+ [CLK_IIS1] = &iis1_clk.common.hw,
+ [CLK_IIS2] = &iis2_clk.common.hw,
+ [CLK_IIS3] = &iis3_clk.common.hw,
+ },
+ .num = CLK_AP_CLK_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_ap_clk_desc = {
+ .clk_clks = sc9860_ap_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks),
+ .hw_clks = &sc9860_ap_clk_hws,
+};
+
+static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m",
+ "ext-rco-100m", "twpll-96m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
+ 0, 3, 8, 2, 0);
+
+static const char * const aux_parents[] = { "ext-32k", "rpll0-26m",
+ "rpll1-26m", "ext-26m",
+ "cppll-50m", "rco-25m",
+ "dpll0-50m", "dpll1-50m",
+ "gpll-42m5", "twpll-48m",
+ "m0-39m", "m1-63m",
+ "l0-38m", "l1-38m" };
+
+static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244,
+ 0, 5, 8, 4, 0);
+
+static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m",
+ "ext-rco-100m", "twpll-96m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
+ 0, 3, 8, 2, 0);
+
+static const char * const cci_parents[] = { "ext-26m", "twpll-384m",
+ "l0-614m4", "twpll-768m" };
+static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310,
+ 0, 2, 8, 2, 0);
+
+static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m",
+ "twpll-307m2", "twpll-384m",
+ "l0-409m6" };
+static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340,
+ 0, 3, 8, 4, 0);
+
+static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c,
+ 8, 1, 0);
+static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334,
+ 8, 1, 0);
+static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c,
+ 8, 1, 0);
+static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344,
+ 8, 1, 0);
+
+static const char * const adi_parents[] = { "rco-4m", "ext-26m",
+ "rco-25m", "twpll-38m4",
+ "twpll-51m2" };
+static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const pwm_parents[] = { "ext-32k", "ext-26m",
+ "rco-4m", "rco-25m",
+ "twpll-48m" };
+static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const efuse_parents[] = { "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m",
+ "rco-100m", "twpll-48m",
+ "twpll-51m2", "twpll-96m",
+ "twpll-128m" };
+static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const thm_parents[] = { "ext-32k", "fac-250k" };
+static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const cm3_i2c_parents[] = { "rco-4m",
+ "ext-26m",
+ "rco-100m",
+ "twpll-48m",
+ "twpll-51m2",
+ "twpll-153m6" };
+static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m",
+ "rco-100m", "twpll-128m",
+ "twpll-153m6", "twpll-192m" };
+static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c,
+ 0, 3, SC9860_MUX_FLAG);
+
+static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m",
+ "rco-100m", "twpll-76m8",
+ "twpll-128m", "twpll-153m6" };
+static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m",
+ "clk-twpll-128m",
+ "clk-twpll-153m6" };
+static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" };
+static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" };
+static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const debounce_parents[] = { "ext-32k", "rco-4m",
+ "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" };
+static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2",
+ "twpll-48m" };
+static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8",
+ "twpll-128m", "twpll-256m" };
+static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324,
+ 0, 2, SC9860_MUX_FLAG);
+
+static struct sprd_clk_common *sc9860_aon_prediv[] = {
+ /* address base is 0x402d0000 */
+ &aon_apb.common,
+ &aux0_clk.common,
+ &aux1_clk.common,
+ &aux2_clk.common,
+ &probe_clk.common,
+ &sp_ahb.common,
+ &cci_clk.common,
+ &gic_clk.common,
+ &cssys_clk.common,
+ &sdio0_2x.common,
+ &sdio1_2x.common,
+ &sdio2_2x.common,
+ &emmc_2x.common,
+ &sdio0_1x.common,
+ &sdio1_1x.common,
+ &sdio2_1x.common,
+ &emmc_1x.common,
+ &adi_clk.common,
+ &pwm0_clk.common,
+ &pwm1_clk.common,
+ &pwm2_clk.common,
+ &pwm3_clk.common,
+ &efuse_clk.common,
+ &cm3_uart0.common,
+ &cm3_uart1.common,
+ &thm_clk.common,
+ &cm3_i2c0.common,
+ &cm3_i2c1.common,
+ &cm4_spi.common,
+ &aon_i2c.common,
+ &avs_clk.common,
+ &ca53_dap.common,
+ &ca53_ts.common,
+ &djtag_tck.common,
+ &pmu_clk.common,
+ &pmu_26m.common,
+ &debounce_clk.common,
+ &otg2_ref.common,
+ &usb3_ref.common,
+ &ap_axi.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {
+ .hws = {
+ [CLK_AON_APB] = &aon_apb.common.hw,
+ [CLK_AUX0] = &aux0_clk.common.hw,
+ [CLK_AUX1] = &aux1_clk.common.hw,
+ [CLK_AUX2] = &aux2_clk.common.hw,
+ [CLK_PROBE] = &probe_clk.common.hw,
+ [CLK_SP_AHB] = &sp_ahb.common.hw,
+ [CLK_CCI] = &cci_clk.common.hw,
+ [CLK_GIC] = &gic_clk.common.hw,
+ [CLK_CSSYS] = &cssys_clk.common.hw,
+ [CLK_SDIO0_2X] = &sdio0_2x.common.hw,
+ [CLK_SDIO1_2X] = &sdio1_2x.common.hw,
+ [CLK_SDIO2_2X] = &sdio2_2x.common.hw,
+ [CLK_EMMC_2X] = &emmc_2x.common.hw,
+ [CLK_SDIO0_1X] = &sdio0_1x.common.hw,
+ [CLK_SDIO1_1X] = &sdio1_1x.common.hw,
+ [CLK_SDIO2_1X] = &sdio2_1x.common.hw,
+ [CLK_EMMC_1X] = &emmc_1x.common.hw,
+ [CLK_ADI] = &adi_clk.common.hw,
+ [CLK_PWM0] = &pwm0_clk.common.hw,
+ [CLK_PWM1] = &pwm1_clk.common.hw,
+ [CLK_PWM2] = &pwm2_clk.common.hw,
+ [CLK_PWM3] = &pwm3_clk.common.hw,
+ [CLK_EFUSE] = &efuse_clk.common.hw,
+ [CLK_CM3_UART0] = &cm3_uart0.common.hw,
+ [CLK_CM3_UART1] = &cm3_uart1.common.hw,
+ [CLK_THM] = &thm_clk.common.hw,
+ [CLK_CM3_I2C0] = &cm3_i2c0.common.hw,
+ [CLK_CM3_I2C1] = &cm3_i2c1.common.hw,
+ [CLK_CM4_SPI] = &cm4_spi.common.hw,
+ [CLK_AON_I2C] = &aon_i2c.common.hw,
+ [CLK_AVS] = &avs_clk.common.hw,
+ [CLK_CA53_DAP] = &ca53_dap.common.hw,
+ [CLK_CA53_TS] = &ca53_ts.common.hw,
+ [CLK_DJTAG_TCK] = &djtag_tck.common.hw,
+ [CLK_PMU] = &pmu_clk.common.hw,
+ [CLK_PMU_26M] = &pmu_26m.common.hw,
+ [CLK_DEBOUNCE] = &debounce_clk.common.hw,
+ [CLK_OTG2_REF] = &otg2_ref.common.hw,
+ [CLK_USB3_REF] = &usb3_ref.common.hw,
+ [CLK_AP_AXI] = &ap_axi.common.hw,
+ },
+ .num = CLK_AON_PREDIV_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aon_prediv_desc = {
+ .clk_clks = sc9860_aon_prediv,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv),
+ .hw_clks = &sc9860_aon_prediv_hws,
+};
+
+static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+
+static struct sprd_clk_common *sc9860_apahb_gate[] = {
+ /* address base is 0x20210000 */
+ &usb3_eb.common,
+ &usb3_suspend.common,
+ &usb3_ref_eb.common,
+ &dma_eb.common,
+ &sdio0_eb.common,
+ &sdio1_eb.common,
+ &sdio2_eb.common,
+ &emmc_eb.common,
+ &rom_eb.common,
+ &busmon_eb.common,
+ &cc63s_eb.common,
+ &cc63p_eb.common,
+ &ce0_eb.common,
+ &ce1_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {
+ .hws = {
+ [CLK_USB3_EB] = &usb3_eb.common.hw,
+ [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw,
+ [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw,
+ [CLK_DMA_EB] = &dma_eb.common.hw,
+ [CLK_SDIO0_EB] = &sdio0_eb.common.hw,
+ [CLK_SDIO1_EB] = &sdio1_eb.common.hw,
+ [CLK_SDIO2_EB] = &sdio2_eb.common.hw,
+ [CLK_EMMC_EB] = &emmc_eb.common.hw,
+ [CLK_ROM_EB] = &rom_eb.common.hw,
+ [CLK_BUSMON_EB] = &busmon_eb.common.hw,
+ [CLK_CC63S_EB] = &cc63s_eb.common.hw,
+ [CLK_CC63P_EB] = &cc63p_eb.common.hw,
+ [CLK_CE0_EB] = &ce0_eb.common.hw,
+ [CLK_CE1_EB] = &ce1_eb.common.hw,
+ },
+ .num = CLK_APAHB_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_apahb_gate_desc = {
+ .clk_clks = sc9860_apahb_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate),
+ .hw_clks = &sc9860_apahb_gate_hws,
+};
+
+static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0,
+ 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0,
+ 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0,
+ 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0,
+ 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4,
+ 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4,
+ 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4,
+ 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4,
+ 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4,
+ 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4,
+ 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4,
+ 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(9), 0, 0);
+
+static struct sprd_clk_common *sc9860_aon_gate[] = {
+ /* address base is 0x402e0000 */
+ &avs_lit_eb.common,
+ &avs_big_eb.common,
+ &ap_intc5_eb.common,
+ &gpio_eb.common,
+ &pwm0_eb.common,
+ &pwm1_eb.common,
+ &pwm2_eb.common,
+ &pwm3_eb.common,
+ &kpd_eb.common,
+ &aon_sys_eb.common,
+ &ap_sys_eb.common,
+ &aon_tmr_eb.common,
+ &ap_tmr0_eb.common,
+ &efuse_eb.common,
+ &eic_eb.common,
+ &pub1_reg_eb.common,
+ &adi_eb.common,
+ &ap_intc0_eb.common,
+ &ap_intc1_eb.common,
+ &ap_intc2_eb.common,
+ &ap_intc3_eb.common,
+ &ap_intc4_eb.common,
+ &splk_eb.common,
+ &mspi_eb.common,
+ &pub0_reg_eb.common,
+ &pin_eb.common,
+ &aon_ckg_eb.common,
+ &gpu_eb.common,
+ &apcpu_ts0_eb.common,
+ &apcpu_ts1_eb.common,
+ &dap_eb.common,
+ &i2c_eb.common,
+ &pmu_eb.common,
+ &thm_eb.common,
+ &aux0_eb.common,
+ &aux1_eb.common,
+ &aux2_eb.common,
+ &probe_eb.common,
+ &gpu0_avs_eb.common,
+ &gpu1_avs_eb.common,
+ &apcpu_wdg_eb.common,
+ &ap_tmr1_eb.common,
+ &ap_tmr2_eb.common,
+ &disp_emc_eb.common,
+ &zip_emc_eb.common,
+ &gsp_emc_eb.common,
+ &osc_aon_eb.common,
+ &lvds_trx_eb.common,
+ &lvds_tcxo_eb.common,
+ &mdar_eb.common,
+ &rtc4m0_cal_eb.common,
+ &rct100m_cal_eb.common,
+ &djtag_eb.common,
+ &mbox_eb.common,
+ &aon_dma_eb.common,
+ &dbg_emc_eb.common,
+ &lvds_pll_div_en.common,
+ &def_eb.common,
+ &aon_apb_rsv0.common,
+ &orp_jtag_eb.common,
+ &vsp_eb.common,
+ &cam_eb.common,
+ &disp_eb.common,
+ &dbg_axi_if_eb.common,
+ &sdio0_2x_en.common,
+ &sdio1_2x_en.common,
+ &sdio2_2x_en.common,
+ &emmc_2x_en.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
+ .hws = {
+ [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw,
+ [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw,
+ [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,
+ [CLK_GPIO_EB] = &gpio_eb.common.hw,
+ [CLK_PWM0_EB] = &pwm0_eb.common.hw,
+ [CLK_PWM1_EB] = &pwm1_eb.common.hw,
+ [CLK_PWM2_EB] = &pwm2_eb.common.hw,
+ [CLK_PWM3_EB] = &pwm3_eb.common.hw,
+ [CLK_KPD_EB] = &kpd_eb.common.hw,
+ [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw,
+ [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw,
+ [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,
+ [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw,
+ [CLK_EFUSE_EB] = &efuse_eb.common.hw,
+ [CLK_EIC_EB] = &eic_eb.common.hw,
+ [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw,
+ [CLK_ADI_EB] = &adi_eb.common.hw,
+ [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,
+ [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,
+ [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,
+ [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,
+ [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,
+ [CLK_SPLK_EB] = &splk_eb.common.hw,
+ [CLK_MSPI_EB] = &mspi_eb.common.hw,
+ [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw,
+ [CLK_PIN_EB] = &pin_eb.common.hw,
+ [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw,
+ [CLK_GPU_EB] = &gpu_eb.common.hw,
+ [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw,
+ [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw,
+ [CLK_DAP_EB] = &dap_eb.common.hw,
+ [CLK_I2C_EB] = &i2c_eb.common.hw,
+ [CLK_PMU_EB] = &pmu_eb.common.hw,
+ [CLK_THM_EB] = &thm_eb.common.hw,
+ [CLK_AUX0_EB] = &aux0_eb.common.hw,
+ [CLK_AUX1_EB] = &aux1_eb.common.hw,
+ [CLK_AUX2_EB] = &aux2_eb.common.hw,
+ [CLK_PROBE_EB] = &probe_eb.common.hw,
+ [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw,
+ [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw,
+ [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw,
+ [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,
+ [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,
+ [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw,
+ [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw,
+ [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw,
+ [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw,
+ [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw,
+ [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw,
+ [CLK_MDAR_EB] = &mdar_eb.common.hw,
+ [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,
+ [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw,
+ [CLK_DJTAG_EB] = &djtag_eb.common.hw,
+ [CLK_MBOX_EB] = &mbox_eb.common.hw,
+ [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw,
+ [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw,
+ [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw,
+ [CLK_DEF_EB] = &def_eb.common.hw,
+ [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw,
+ [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw,
+ [CLK_VSP_EB] = &vsp_eb.common.hw,
+ [CLK_CAM_EB] = &cam_eb.common.hw,
+ [CLK_DISP_EB] = &disp_eb.common.hw,
+ [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw,
+ [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw,
+ [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
+ [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
+ [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
+ },
+ .num = CLK_AON_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aon_gate_desc = {
+ .clk_clks = sc9860_aon_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate),
+ .hw_clks = &sc9860_aon_gate_hws,
+};
+
+static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };
+static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m",
+ "twpll-768m", "ltepll0",
+ "twpll", "mpll0" };
+static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20,
+ mcu_table, 0, 4, 4, 3, 0);
+
+static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m",
+ "twpll-768m", "ltepll0",
+ "twpll", "mpll1" };
+static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24,
+ mcu_table, 0, 4, 4, 3, 0);
+
+static struct sprd_clk_common *sc9860_aonsecure_clk[] = {
+ /* address base is 0x40880000 */
+ &lit_mcu.common,
+ &big_mcu.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {
+ .hws = {
+ [CLK_LIT_MCU] = &lit_mcu.common.hw,
+ [CLK_BIG_MCU] = &big_mcu.common.hw,
+ },
+ .num = CLK_AONSECURE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {
+ .clk_clks = sc9860_aonsecure_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk),
+ .hw_clks = &sc9860_aonsecure_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb",
+ 0x0, 0x100, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb",
+ 0x0, 0x100, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb",
+ 0x0, 0x100, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb",
+ 0x0, 0x100, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb",
+ 0x0, 0x100, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb",
+ 0x0, 0x100, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb",
+ 0x0, 0x100, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb",
+ 0x0, 0x100, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb",
+ 0x0, 0x100, BIT(11), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb",
+ 0x0, 0x100, BIT(12), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb",
+ 0x0, 0x100, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb",
+ 0x0, 0x100, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb",
+ 0x0, 0x100, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb",
+ 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb",
+ 0x0, 0x100, BIT(17), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb",
+ 0x0, 0x100, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb",
+ 0x0, 0x100, BIT(19), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb",
+ 0x0, 0x100, BIT(20), 0, 0);
+
+static struct sprd_clk_common *sc9860_agcp_gate[] = {
+ /* address base is 0x415e0000 */
+ &agcp_iis0_eb.common,
+ &agcp_iis1_eb.common,
+ &agcp_iis2_eb.common,
+ &agcp_iis3_eb.common,
+ &agcp_uart_eb.common,
+ &agcp_dmacp_eb.common,
+ &agcp_dmaap_eb.common,
+ &agcp_arc48k_eb.common,
+ &agcp_src44p1k_eb.common,
+ &agcp_mcdt_eb.common,
+ &agcp_vbcifd_eb.common,
+ &agcp_vbc_eb.common,
+ &agcp_spinlock_eb.common,
+ &agcp_icu_eb.common,
+ &agcp_ap_ashb_eb.common,
+ &agcp_cp_ashb_eb.common,
+ &agcp_aud_eb.common,
+ &agcp_audif_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {
+ .hws = {
+ [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw,
+ [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw,
+ [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw,
+ [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw,
+ [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw,
+ [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw,
+ [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw,
+ [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw,
+ [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw,
+ [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw,
+ [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw,
+ [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw,
+ [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw,
+ [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw,
+ [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw,
+ [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw,
+ [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw,
+ [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw,
+ },
+ .num = CLK_AGCP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_agcp_gate_desc = {
+ .clk_clks = sc9860_agcp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate),
+ .hw_clks = &sc9860_agcp_gate_hws,
+};
+
+static const char * const gpu_parents[] = { "twpll-512m",
+ "twpll-768m",
+ "gpll" };
+static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20,
+ 0, 2, 8, 4, 0);
+
+static struct sprd_clk_common *sc9860_gpu_clk[] = {
+ /* address base is 0x60200000 */
+ &gpu_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {
+ .hws = {
+ [CLK_GPU] = &gpu_clk.common.hw,
+ },
+ .num = CLK_GPU_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_gpu_clk_desc = {
+ .clk_clks = sc9860_gpu_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk),
+ .hw_clks = &sc9860_gpu_clk_hws,
+};
+
+static const char * const ahb_parents[] = { "ext-26m", "twpll-96m",
+ "twpll-128m", "twpll-153m6" };
+static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m",
+ "twpll-256m", "twpll-307m2",
+ "twpll-384m" };
+static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0);
+
+static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m",
+ "twpll-256m", "twpll-307m2" };
+static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0);
+
+static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6",
+ "twpll-192m", "twpll-256m" };
+static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c,
+ 0, 2, SC9860_MUX_FLAG);
+static const char * const vsp_26m_parents[] = { "ext-26m" };
+static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30,
+ 0, 1, SC9860_MUX_FLAG);
+
+static struct sprd_clk_common *sc9860_vsp_clk[] = {
+ /* address base is 0x61000000 */
+ &ahb_vsp.common,
+ &vsp_clk.common,
+ &vsp_enc.common,
+ &vpp_clk.common,
+ &vsp_26m.common,
+};
+
+static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {
+ .hws = {
+ [CLK_AHB_VSP] = &ahb_vsp.common.hw,
+ [CLK_VSP] = &vsp_clk.common.hw,
+ [CLK_VSP_ENC] = &vsp_enc.common.hw,
+ [CLK_VPP] = &vpp_clk.common.hw,
+ [CLK_VSP_26M] = &vsp_26m.common.hw,
+ },
+ .num = CLK_VSP_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_vsp_clk_desc = {
+ .clk_clks = sc9860_vsp_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk),
+ .hw_clks = &sc9860_vsp_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8,
+ BIT(10), 0, 0);
+
+static struct sprd_clk_common *sc9860_vsp_gate[] = {
+ /* address base is 0x61100000 */
+ &vsp_dec_eb.common,
+ &vsp_ckg_eb.common,
+ &vsp_mmu_eb.common,
+ &vsp_enc_eb.common,
+ &vpp_eb.common,
+ &vsp_26m_eb.common,
+ &vsp_axi_gate.common,
+ &vsp_enc_gate.common,
+ &vpp_axi_gate.common,
+ &vsp_bm_gate.common,
+ &vsp_enc_bm_gate.common,
+ &vpp_bm_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {
+ .hws = {
+ [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw,
+ [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw,
+ [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw,
+ [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw,
+ [CLK_VPP_EB] = &vpp_eb.common.hw,
+ [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw,
+ [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw,
+ [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw,
+ [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw,
+ [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw,
+ [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw,
+ [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw,
+ },
+ .num = CLK_VSP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_vsp_gate_desc = {
+ .clk_clks = sc9860_vsp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate),
+ .hw_clks = &sc9860_vsp_gate_hws,
+};
+
+static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+static const char * const sensor_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-76m8", "twpll-96m" };
+static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c,
+ 0, 2, 8, 3, 0);
+static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c,
+ BIT(16), 0, 0);
+static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50,
+ BIT(16), 0, 0);
+
+static struct sprd_clk_common *sc9860_cam_clk[] = {
+ /* address base is 0x62000000 */
+ &ahb_cam.common,
+ &sensor0_clk.common,
+ &sensor1_clk.common,
+ &sensor2_clk.common,
+ &mipi_csi0_eb.common,
+ &mipi_csi1_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_cam_clk_hws = {
+ .hws = {
+ [CLK_AHB_CAM] = &ahb_cam.common.hw,
+ [CLK_SENSOR0] = &sensor0_clk.common.hw,
+ [CLK_SENSOR1] = &sensor1_clk.common.hw,
+ [CLK_SENSOR2] = &sensor2_clk.common.hw,
+ [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw,
+ [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw,
+ },
+ .num = CLK_CAM_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_cam_clk_desc = {
+ .clk_clks = sc9860_cam_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk),
+ .hw_clks = &sc9860_cam_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(9), 0, 0);
+static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(11), 0, 0);
+static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(12), 0, 0);
+static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(16), 0, 0);
+static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(17), 0, 0);
+static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(19), 0, 0);
+static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(20), 0, 0);
+static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(21), 0, 0);
+static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8,
+ BIT(3), 0, 0);
+static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8,
+ BIT(4), 0, 0);
+static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8,
+ BIT(5), 0, 0);
+static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8,
+ BIT(6), 0, 0);
+static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8,
+ BIT(7), 0, 0);
+static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8,
+ BIT(10), 0, 0);
+static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8,
+ BIT(11), 0, 0);
+static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8,
+ BIT(12), 0, 0);
+static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8,
+ BIT(13), 0, 0);
+static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8,
+ BIT(14), 0, 0);
+static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8,
+ BIT(15), 0, 0);
+static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8,
+ BIT(16), 0, 0);
+static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8,
+ BIT(17), 0, 0);
+static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8,
+ BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(9), 0, 0);
+
+static struct sprd_clk_common *sc9860_cam_gate[] = {
+ /* address base is 0x62100000 */
+ &dcam0_eb.common,
+ &dcam1_eb.common,
+ &isp0_eb.common,
+ &csi0_eb.common,
+ &csi1_eb.common,
+ &jpg0_eb.common,
+ &jpg1_eb.common,
+ &cam_ckg_eb.common,
+ &cam_mmu_eb.common,
+ &isp1_eb.common,
+ &cpp_eb.common,
+ &mmu_pf_eb.common,
+ &isp2_eb.common,
+ &dcam2isp_if_eb.common,
+ &isp2dcam_if_eb.common,
+ &isp_lclk_eb.common,
+ &isp_iclk_eb.common,
+ &isp_mclk_eb.common,
+ &isp_pclk_eb.common,
+ &isp_isp2dcam_eb.common,
+ &dcam0_if_eb.common,
+ &clk26m_if_eb.common,
+ &cphy0_gate.common,
+ &mipi_csi0_gate.common,
+ &cphy1_gate.common,
+ &mipi_csi1.common,
+ &dcam0_axi_gate.common,
+ &dcam1_axi_gate.common,
+ &sensor0_gate.common,
+ &sensor1_gate.common,
+ &jpg0_axi_gate.common,
+ &gpg1_axi_gate.common,
+ &isp0_axi_gate.common,
+ &isp1_axi_gate.common,
+ &isp2_axi_gate.common,
+ &cpp_axi_gate.common,
+ &d0_if_axi_gate.common,
+ &d2i_if_axi_gate.common,
+ &i2d_if_axi_gate.common,
+ &spare_axi_gate.common,
+ &sensor2_gate.common,
+ &d0if_in_d_en.common,
+ &d1if_in_d_en.common,
+ &d0if_in_d2i_en.common,
+ &d1if_in_d2i_en.common,
+ &ia_in_d2i_en.common,
+ &ib_in_d2i_en.common,
+ &ic_in_d2i_en.common,
+ &ia_in_i_en.common,
+ &ib_in_i_en.common,
+ &ic_in_i_en.common,
+};
+
+static struct clk_hw_onecell_data sc9860_cam_gate_hws = {
+ .hws = {
+ [CLK_DCAM0_EB] = &dcam0_eb.common.hw,
+ [CLK_DCAM1_EB] = &dcam1_eb.common.hw,
+ [CLK_ISP0_EB] = &isp0_eb.common.hw,
+ [CLK_CSI0_EB] = &csi0_eb.common.hw,
+ [CLK_CSI1_EB] = &csi1_eb.common.hw,
+ [CLK_JPG0_EB] = &jpg0_eb.common.hw,
+ [CLK_JPG1_EB] = &jpg1_eb.common.hw,
+ [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw,
+ [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw,
+ [CLK_ISP1_EB] = &isp1_eb.common.hw,
+ [CLK_CPP_EB] = &cpp_eb.common.hw,
+ [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw,
+ [CLK_ISP2_EB] = &isp2_eb.common.hw,
+ [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw,
+ [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw,
+ [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw,
+ [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw,
+ [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw,
+ [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw,
+ [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw,
+ [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw,
+ [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw,
+ [CLK_CPHY0_GATE] = &cphy0_gate.common.hw,
+ [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw,
+ [CLK_CPHY1_GATE] = &cphy1_gate.common.hw,
+ [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
+ [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw,
+ [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw,
+ [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw,
+ [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw,
+ [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw,
+ [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw,
+ [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw,
+ [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw,
+ [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw,
+ [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw,
+ [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw,
+ [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw,
+ [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw,
+ [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw,
+ [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw,
+ [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw,
+ [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw,
+ [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw,
+ [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw,
+ [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw,
+ [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw,
+ [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw,
+ [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw,
+ [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw,
+ [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw,
+ },
+ .num = CLK_CAM_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_cam_gate_desc = {
+ .clk_clks = sc9860_cam_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate),
+ .hw_clks = &sc9860_cam_gate_hws,
+};
+
+static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40,
+ 0, 2, 8, 2, 0);
+
+static struct sprd_clk_common *sc9860_disp_clk[] = {
+ /* address base is 0x63000000 */
+ &ahb_disp.common,
+ &dispc0_dpi.common,
+ &dispc1_dpi.common,
+};
+
+static struct clk_hw_onecell_data sc9860_disp_clk_hws = {
+ .hws = {
+ [CLK_AHB_DISP] = &ahb_disp.common.hw,
+ [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw,
+ [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw,
+ },
+ .num = CLK_DISP_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_disp_clk_desc = {
+ .clk_clks = sc9860_disp_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk),
+ .hw_clks = &sc9860_disp_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(9), 0, 0);
+static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(16), 0, 0);
+static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8,
+ BIT(3), 0, 0);
+static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8,
+ BIT(4), 0, 0);
+static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8,
+ BIT(5), 0, 0);
+static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8,
+ BIT(6), 0, 0);
+static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8,
+ BIT(7), 0, 0);
+static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8,
+ BIT(10), 0, 0);
+static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8,
+ BIT(11), 0, 0);
+static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8,
+ BIT(12), 0, 0);
+static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8,
+ BIT(13), 0, 0);
+static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8,
+ BIT(14), 0, 0);
+static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8,
+ BIT(15), 0, 0);
+
+static struct sprd_clk_common *sc9860_disp_gate[] = {
+ /* address base is 0x63100000 */
+ &dispc0_eb.common,
+ &dispc1_eb.common,
+ &dispc_mmu_eb.common,
+ &gsp0_eb.common,
+ &gsp1_eb.common,
+ &gsp0_mmu_eb.common,
+ &gsp1_mmu_eb.common,
+ &dsi0_eb.common,
+ &dsi1_eb.common,
+ &disp_ckg_eb.common,
+ &disp_gpu_eb.common,
+ &gpu_mtx_eb.common,
+ &gsp_mtx_eb.common,
+ &tmc_mtx_eb.common,
+ &dispc_mtx_eb.common,
+ &dphy0_gate.common,
+ &dphy1_gate.common,
+ &gsp0_a_gate.common,
+ &gsp1_a_gate.common,
+ &gsp0_f_gate.common,
+ &gsp1_f_gate.common,
+ &d_mtx_f_gate.common,
+ &d_mtx_a_gate.common,
+ &d_noc_f_gate.common,
+ &d_noc_a_gate.common,
+ &gsp_mtx_f_gate.common,
+ &gsp_mtx_a_gate.common,
+ &gsp_noc_f_gate.common,
+ &gsp_noc_a_gate.common,
+ &dispm0idle_gate.common,
+ &gspm0idle_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_disp_gate_hws = {
+ .hws = {
+ [CLK_DISPC0_EB] = &dispc0_eb.common.hw,
+ [CLK_DISPC1_EB] = &dispc1_eb.common.hw,
+ [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw,
+ [CLK_GSP0_EB] = &gsp0_eb.common.hw,
+ [CLK_GSP1_EB] = &gsp1_eb.common.hw,
+ [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw,
+ [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw,
+ [CLK_DSI0_EB] = &dsi0_eb.common.hw,
+ [CLK_DSI1_EB] = &dsi1_eb.common.hw,
+ [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw,
+ [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw,
+ [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw,
+ [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw,
+ [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw,
+ [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw,
+ [CLK_DPHY0_GATE] = &dphy0_gate.common.hw,
+ [CLK_DPHY1_GATE] = &dphy1_gate.common.hw,
+ [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw,
+ [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw,
+ [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw,
+ [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw,
+ [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw,
+ [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw,
+ [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw,
+ [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw,
+ [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw,
+ [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw,
+ [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw,
+ [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw,
+ [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw,
+ [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw,
+ },
+ .num = CLK_DISP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_disp_gate_desc = {
+ .clk_clks = sc9860_disp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate),
+ .hw_clks = &sc9860_disp_gate_hws,
+};
+
+static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+
+static struct sprd_clk_common *sc9860_apapb_gate[] = {
+ /* address base is 0x70b00000 */
+ &sim0_eb.common,
+ &iis0_eb.common,
+ &iis1_eb.common,
+ &iis2_eb.common,
+ &iis3_eb.common,
+ &spi0_eb.common,
+ &spi1_eb.common,
+ &spi2_eb.common,
+ &i2c0_eb.common,
+ &i2c1_eb.common,
+ &i2c2_eb.common,
+ &i2c3_eb.common,
+ &i2c4_eb.common,
+ &i2c5_eb.common,
+ &uart0_eb.common,
+ &uart1_eb.common,
+ &uart2_eb.common,
+ &uart3_eb.common,
+ &uart4_eb.common,
+ &ap_ckg_eb.common,
+ &spi3_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {
+ .hws = {
+ [CLK_SIM0_EB] = &sim0_eb.common.hw,
+ [CLK_IIS0_EB] = &iis0_eb.common.hw,
+ [CLK_IIS1_EB] = &iis1_eb.common.hw,
+ [CLK_IIS2_EB] = &iis2_eb.common.hw,
+ [CLK_IIS3_EB] = &iis3_eb.common.hw,
+ [CLK_SPI0_EB] = &spi0_eb.common.hw,
+ [CLK_SPI1_EB] = &spi1_eb.common.hw,
+ [CLK_SPI2_EB] = &spi2_eb.common.hw,
+ [CLK_I2C0_EB] = &i2c0_eb.common.hw,
+ [CLK_I2C1_EB] = &i2c1_eb.common.hw,
+ [CLK_I2C2_EB] = &i2c2_eb.common.hw,
+ [CLK_I2C3_EB] = &i2c3_eb.common.hw,
+ [CLK_I2C4_EB] = &i2c4_eb.common.hw,
+ [CLK_I2C5_EB] = &i2c5_eb.common.hw,
+ [CLK_UART0_EB] = &uart0_eb.common.hw,
+ [CLK_UART1_EB] = &uart1_eb.common.hw,
+ [CLK_UART2_EB] = &uart2_eb.common.hw,
+ [CLK_UART3_EB] = &uart3_eb.common.hw,
+ [CLK_UART4_EB] = &uart4_eb.common.hw,
+ [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw,
+ [CLK_SPI3_EB] = &spi3_eb.common.hw,
+ },
+ .num = CLK_APAPB_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_apapb_gate_desc = {
+ .clk_clks = sc9860_apapb_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate),
+ .hw_clks = &sc9860_apapb_gate_hws,
+};
+
+static const struct of_device_id sprd_sc9860_clk_ids[] = {
+ { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */
+ .data = &sc9860_pmu_gate_desc },
+ { .compatible = "sprd,sc9860-pll", /* 0x4040 */
+ .data = &sc9860_pll_desc },
+ { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */
+ .data = &sc9860_ap_clk_desc },
+ { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */
+ .data = &sc9860_aon_prediv_desc },
+ { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */
+ .data = &sc9860_apahb_gate_desc },
+ { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */
+ .data = &sc9860_aon_gate_desc },
+ { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */
+ .data = &sc9860_aonsecure_clk_desc },
+ { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */
+ .data = &sc9860_agcp_gate_desc },
+ { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */
+ .data = &sc9860_gpu_clk_desc },
+ { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */
+ .data = &sc9860_vsp_clk_desc },
+ { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */
+ .data = &sc9860_vsp_gate_desc },
+ { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */
+ .data = &sc9860_cam_clk_desc },
+ { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */
+ .data = &sc9860_cam_gate_desc },
+ { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */
+ .data = &sc9860_disp_clk_desc },
+ { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */
+ .data = &sc9860_disp_gate_desc },
+ { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */
+ .data = &sc9860_apapb_gate_desc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);
+
+static int sc9860_clk_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ const struct sprd_clk_desc *desc;
+
+ match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);
+ if (!match) {
+ pr_err("%s: of_match_node() failed", __func__);
+ return -ENODEV;
+ }
+
+ desc = match->data;
+ sprd_clk_regmap_init(pdev, desc);
+
+ return sprd_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static struct platform_driver sc9860_clk_driver = {
+ .probe = sc9860_clk_probe,
+ .driver = {
+ .name = "sc9860-clk",
+ .of_match_table = sprd_sc9860_clk_ids,
+ },
+};
+module_platform_driver(sc9860_clk_driver);
+
+MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:sc9860-clk");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 2bb4cabf802f..ee9c12cf3f08 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -400,28 +400,45 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
BIT(31), /* gate */
0);
+/*
+ * MMC clocks are the new timing mode (see A83T & H3) variety, but without
+ * the mode switch. This means they have a 2x post divider between the clock
+ * and the MMC module. This is not documented in the manual, but is taken
+ * into consideration when setting the mmc module clocks in the BSP kernel.
+ * Without it, MMC performance is degraded.
+ *
+ * We model it here to be consistent with other SoCs supporting this mode.
+ * The alternative would be to add the 2x multiplier when setting the MMC
+ * module clock in the MMC driver, just for the A64.
+ */
static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
"pll-periph1-2x" };
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088,
- 0, 4, /* M */
- 16, 2, /* P */
- 24, 2, /* mux */
- BIT(31), /* gate */
- 0);
-
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c,
- 0, 4, /* M */
- 16, 2, /* P */
- 24, 2, /* mux */
- BIT(31), /* gate */
- 0);
-
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090,
- 0, 4, /* M */
- 16, 2, /* P */
- 24, 2, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
+ mmc_default_parents, 0x088,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
+ mmc_default_parents, 0x08c,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
+ mmc_default_parents, 0x090,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 5cedcd0d8be8..7d08015b980d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -76,15 +76,26 @@ static struct ccu_mult pll_c1cpux_clk = {
*/
#define SUN8I_A83T_PLL_AUDIO_REG 0x008
+/* clock rates doubled for post divider */
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+ { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
+ { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
+};
+
static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(0, 6),
+ .fixed_post_div = 2,
+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
+ 0x284, BIT(31)),
.common = {
.reg = SUN8I_A83T_PLL_AUDIO_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
- .features = CCU_FEATURE_LOCK_REG,
+ .features = CCU_FEATURE_LOCK_REG |
+ CCU_FEATURE_FIXED_POSTDIV |
+ CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-audio", "osc24M",
&ccu_nm_ops, CLK_SET_RATE_UNGATE),
},
@@ -493,8 +504,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const tcon1_parents[] = { "pll-video1" };
-static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,
- 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
+ 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
@@ -889,9 +900,10 @@ static int sun8i_a83t_ccu_probe(struct platform_device *pdev)
if (IS_ERR(reg))
return PTR_ERR(reg);
- /* Enforce d1 = 0, d2 = 0 for Audio PLL */
+ /* Enforce d1 = 0, d2 = 1 for Audio PLL */
val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG);
- val &= ~(BIT(16) | BIT(18));
+ val &= ~BIT(16);
+ val |= BIT(18);
writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cc9d9952121..468d1abaf0ee 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
@@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
&wb_div_a83_clk.common,
};
+static struct ccu_common *sun8i_h3_de2_clks[] = {
+ &mixer0_clk.common,
+ &mixer1_clk.common,
+ &wb_clk.common,
+
+ &bus_mixer0_clk.common,
+ &bus_mixer1_clk.common,
+ &bus_wb_clk.common,
+
+ &mixer0_div_clk.common,
+ &mixer1_div_clk.common,
+ &wb_div_clk.common,
+};
+
static struct ccu_common *sun8i_v3s_de2_clks[] = {
&mixer0_clk.common,
&wb_clk.common,
@@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
.num = CLK_NUMBER,
};
+static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
+ .hws = {
+ [CLK_MIXER0] = &mixer0_clk.common.hw,
+ [CLK_MIXER1] = &mixer1_clk.common.hw,
+ [CLK_WB] = &wb_clk.common.hw,
+
+ [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
+ [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
+ [CLK_BUS_WB] = &bus_wb_clk.common.hw,
+
+ [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
+ [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
+ [CLK_WB_DIV] = &wb_div_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
@@ -133,11 +166,21 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
+static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+
+ .hw_clks = &sun8i_h3_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
- .ccu_clks = sun8i_a83t_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
- .hw_clks = &sun8i_a83t_de2_hw_clks,
+ .hw_clks = &sun8i_h3_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
@@ -238,6 +281,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.data = &sun8i_a83t_de2_clk_desc,
},
{
+ .compatible = "allwinner,sun8i-h3-de2-clk",
+ .data = &sun8i_h3_de2_clk_desc,
+ },
+ {
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = &sun8i_v3s_de2_clk_desc,
},
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index 5d684ce77c54..568cfaed0813 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -31,35 +31,6 @@
struct device_node;
-#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
- &(struct clk_init_data) { \
- .flags = _flags, \
- .name = _name, \
- .parent_names = (const char *[]) { _parent }, \
- .num_parents = 1, \
- .ops = _ops, \
- }
-
-#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
- &(struct clk_init_data) { \
- .flags = _flags, \
- .name = _name, \
- .parent_names = _parents, \
- .num_parents = ARRAY_SIZE(_parents), \
- .ops = _ops, \
- }
-
-#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
- _div, _mult, _flags) \
- struct clk_fixed_factor _struct = { \
- .div = _div, \
- .mult = _mult, \
- .hw.init = CLK_HW_INIT(_name, \
- _parent, \
- &clk_fixed_factor_ops, \
- _flags), \
- }
-
struct ccu_common {
void __iomem *base;
u16 reg;
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index baa3cf96507b..302a18efd39f 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -71,7 +71,7 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
parent_rate);
val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
- cd->div.flags);
+ cd->div.flags, cd->div.width);
if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
val /= cd->fixed_post_div;
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 688855e7dc8c..5d0af4051737 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -50,12 +50,19 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
unsigned int max_m, max_p;
unsigned int m, p;
+ if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate *= cmp->fixed_post_div;
+
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
+ rate = *parent_rate / p / m;
+
+ if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= cmp->fixed_post_div;
- return *parent_rate / p / m;
+ return rate;
}
static void ccu_mp_disable(struct clk_hw *hw)
@@ -83,6 +90,7 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
+ unsigned long rate;
unsigned int m, p;
u32 reg;
@@ -101,7 +109,11 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
p = reg >> cmp->p.shift;
p &= (1 << cmp->p.width) - 1;
- return (parent_rate >> p) / m;
+ rate = (parent_rate >> p) / m;
+ if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= cmp->fixed_post_div;
+
+ return rate;
}
static int ccu_mp_determine_rate(struct clk_hw *hw,
@@ -129,6 +141,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+ /* Adjust target rate according to post-dividers */
+ if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate * cmp->fixed_post_div;
+
ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
spin_lock_irqsave(cmp->common.lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h
index aaef11d747ea..5107635e61de 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.h
+++ b/drivers/clk/sunxi-ng/ccu_mp.h
@@ -33,9 +33,33 @@ struct ccu_mp {
struct ccu_div_internal m;
struct ccu_div_internal p;
struct ccu_mux_internal mux;
+
+ unsigned int fixed_post_div;
+
struct ccu_common common;
};
+#define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \
+ _mshift, _mwidth, \
+ _pshift, _pwidth, \
+ _muxshift, _muxwidth, \
+ _gate, _postdiv, _flags) \
+ struct ccu_mp _struct = { \
+ .enable = _gate, \
+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
+ .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
+ .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
+ .fixed_post_div = _postdiv, \
+ .common = { \
+ .reg = _reg, \
+ .features = CCU_FEATURE_FIXED_POSTDIV, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parents, \
+ &ccu_mp_ops, \
+ _flags), \
+ } \
+ }
+
#define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 7620aa973a6e..a16de092bf94 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -70,11 +70,18 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
+ unsigned long rate;
unsigned long n, m;
u32 reg;
- if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac))
- return ccu_frac_helper_read_rate(&nm->common, &nm->frac);
+ if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac)) {
+ rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac);
+
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nm->fixed_post_div;
+
+ return rate;
+ }
reg = readl(nm->common.base + nm->common.reg);
@@ -90,15 +97,15 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
if (!m)
m++;
- if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm)) {
- unsigned long rate =
- ccu_sdm_helper_read_rate(&nm->common, &nm->sdm,
- m, n);
- if (rate)
- return rate;
- }
+ if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm))
+ rate = ccu_sdm_helper_read_rate(&nm->common, &nm->sdm, m, n);
+ else
+ rate = parent_rate * n / m;
+
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nm->fixed_post_div;
- return parent_rate * n / m;
+ return rate;
}
static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -107,11 +114,20 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
- if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate *= nm->fixed_post_div;
+
+ if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nm->fixed_post_div;
return rate;
+ }
- if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate))
+ if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nm->fixed_post_div;
return rate;
+ }
_nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
@@ -119,8 +135,12 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
ccu_nm_find_best(*parent_rate, rate, &_nm);
+ rate = *parent_rate * _nm.n / _nm.m;
+
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nm->fixed_post_div;
- return *parent_rate * _nm.n / _nm.m;
+ return rate;
}
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -131,6 +151,10 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long flags;
u32 reg;
+ /* Adjust target rate according to post-dividers */
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate * nm->fixed_post_div;
+
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
spin_lock_irqsave(nm->common.lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index c623b0c7a23c..eba586b4c7d0 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -36,6 +36,8 @@ struct ccu_nm {
struct ccu_frac_internal frac;
struct ccu_sdm_internal sdm;
+ unsigned int fixed_post_div;
+
struct ccu_common common;
};
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 856fef65433b..661a73284e9f 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -176,10 +176,10 @@ static const struct clk_ops clk_factors_ops = {
.set_rate = clk_factors_set_rate,
};
-struct clk *sunxi_factors_register(struct device_node *node,
- const struct factors_data *data,
- spinlock_t *lock,
- void __iomem *reg)
+static struct clk *__sunxi_factors_register(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock, void __iomem *reg,
+ unsigned long flags)
{
struct clk *clk;
struct clk_factors *factors;
@@ -249,7 +249,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
parents, i,
mux_hw, &clk_mux_ops,
&factors->hw, &clk_factors_ops,
- gate_hw, &clk_gate_ops, 0);
+ gate_hw, &clk_gate_ops, CLK_IS_CRITICAL);
if (IS_ERR(clk))
goto err_register;
@@ -272,6 +272,22 @@ err_factors:
return NULL;
}
+struct clk *sunxi_factors_register(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg)
+{
+ return __sunxi_factors_register(node, data, lock, reg, 0);
+}
+
+struct clk *sunxi_factors_register_critical(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg)
+{
+ return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL);
+}
+
void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
{
struct clk_hw *hw = __clk_get_hw(clk);
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 824f746b2567..7ad2ca924d0d 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -55,6 +55,10 @@ struct clk *sunxi_factors_register(struct device_node *node,
const struct factors_data *data,
spinlock_t *lock,
void __iomem *reg);
+struct clk *sunxi_factors_register_critical(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg);
void sunxi_factors_unregister(struct device_node *node, struct clk *clk);
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4417ae129ac7..a27c264cc9b4 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -15,7 +15,6 @@
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
@@ -155,7 +154,6 @@ static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
static void __init sun5i_a13_mbus_setup(struct device_node *node)
{
- struct clk *mbus;
void __iomem *reg;
reg = of_iomap(node, 0);
@@ -164,12 +162,9 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
return;
}
- mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
- &sun5i_a13_mbus_lock, reg);
-
/* The MBUS clocks needs to be always enabled */
- __clk_get(mbus);
- clk_prepare_enable(mbus);
+ sunxi_factors_register_critical(node, &sun4i_a10_mod0_data,
+ &sun5i_a13_mbus_lock, reg);
}
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
index ea1eed24778c..d5c31804ee54 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -98,10 +98,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg);
clk = sun8i_a23_apb0_register(np, reg);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- return 0;
+ return PTR_ERR_OR_ZERO(clk);
}
static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
diff --git a/drivers/clk/sunxi/clk-sun8i-mbus.c b/drivers/clk/sunxi/clk-sun8i-mbus.c
index b200ebf159ee..56db89b6979f 100644
--- a/drivers/clk/sunxi/clk-sun8i-mbus.c
+++ b/drivers/clk/sunxi/clk-sun8i-mbus.c
@@ -15,7 +15,6 @@
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@@ -82,11 +81,12 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
mux->mask = SUN8I_MBUS_MUX_MASK;
mux->lock = &sun8i_a23_mbus_lock;
+ /* The MBUS clocks needs to be always enabled */
clk = clk_register_composite(NULL, clk_name, parents, num_parents,
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
- 0);
+ CLK_IS_CRITICAL);
if (IS_ERR(clk))
goto err_free_gate;
@@ -95,9 +95,6 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
goto err_unregister_clk;
kfree(parents); /* parents is deep copied */
- /* The MBUS clocks needs to be always enabled */
- __clk_get(clk);
- clk_prepare_enable(clk);
return;
diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
index 43f014f85803..e9295c286d5d 100644
--- a/drivers/clk/sunxi/clk-sun9i-core.c
+++ b/drivers/clk/sunxi/clk-sun9i-core.c
@@ -15,7 +15,6 @@
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -140,7 +139,6 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
static void __init sun9i_a80_gt_setup(struct device_node *node)
{
void __iomem *reg;
- struct clk *gt;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
@@ -149,12 +147,9 @@ static void __init sun9i_a80_gt_setup(struct device_node *node)
return;
}
- gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
- &sun9i_a80_gt_lock, reg);
-
/* The GT bus clock needs to be always enabled */
- __clk_get(gt);
- clk_prepare_enable(gt);
+ sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
+ &sun9i_a80_gt_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index aa4add580516..012714d94b42 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -656,7 +656,8 @@ static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
};
static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
- const struct mux_data *data)
+ const struct mux_data *data,
+ unsigned long flags)
{
struct clk *clk;
const char *clk_name = node->name;
@@ -678,7 +679,7 @@ static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
}
clk = clk_register_mux(NULL, clk_name, parents, i,
- CLK_SET_RATE_PARENT, reg,
+ CLK_SET_RATE_PARENT | flags, reg,
data->shift, SUNXI_MUX_GATE_WIDTH,
0, &clk_lock);
@@ -703,29 +704,22 @@ out_unmap:
static void __init sun4i_cpu_clk_setup(struct device_node *node)
{
- struct clk *clk;
-
- clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
- if (!clk)
- return;
-
/* Protect CPU clock */
- __clk_get(clk);
- clk_prepare_enable(clk);
+ sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
}
CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
sun4i_cpu_clk_setup);
static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
{
- sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
+ sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
}
CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
sun6i_ahb1_mux_clk_setup);
static void __init sun8i_ahb2_clk_setup(struct device_node *node)
{
- sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
+ sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
}
CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
sun8i_ahb2_clk_setup);
@@ -900,6 +894,7 @@ struct divs_data {
u8 shift; /* otherwise it's a normal divisor with this shift */
u8 pow; /* is it power-of-two based? */
u8 gate; /* is it independently gateable? */
+ bool critical;
} div[SUNXI_DIVS_MAX_QTY];
};
@@ -915,7 +910,8 @@ static const struct divs_data pll5_divs_data __initconst = {
.factors = &sun4i_pll5_data,
.ndivs = 2,
.div = {
- { .shift = 0, .pow = 0, }, /* M, DDR */
+ /* Protect PLL5_DDR */
+ { .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
{ .shift = 16, .pow = 1, }, /* P, other */
/* No output for the base factor clock */
}
@@ -1089,7 +1085,9 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
NULL, NULL,
rate_hw, rate_ops,
gate_hw, &clk_gate_ops,
- clkflags);
+ clkflags |
+ data->div[i].critical ?
+ CLK_IS_CRITICAL : 0);
WARN_ON(IS_ERR(clk_data->clks[i]));
}
@@ -1117,15 +1115,7 @@ out_unmap:
static void __init sun4i_pll5_clk_setup(struct device_node *node)
{
- struct clk **clks;
-
- clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
- if (!clks)
- return;
-
- /* Protect PLL5_DDR */
- __clk_get(clks[0]);
- clk_prepare_enable(clks[0]);
+ sunxi_divs_clk_setup(node, &pll5_divs_data);
}
CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
sun4i_pll5_clk_setup);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a2293ee09440..5ab295d2a3cb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -19,10 +19,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
clk-dra7-atl.o dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
-ifdef CONFIG_ATAGS
-obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
-endif
-
endif # CONFIG_ARCH_OMAP2PLUS
obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
deleted file mode 100644
index 0fbf8a917955..000000000000
--- a/drivers/clk/ti/clk-3xxx-legacy.c
+++ /dev/null
@@ -1,4656 +0,0 @@
-/*
- * OMAP3 Legacy clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc
- * Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/ti.h>
-
-#include "clock.h"
-
-static struct ti_clk_fixed virt_12m_ck_data = {
- .frequency = 12000000,
-};
-
-static struct ti_clk virt_12m_ck = {
- .name = "virt_12m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_12m_ck_data,
-};
-
-static struct ti_clk_fixed virt_13m_ck_data = {
- .frequency = 13000000,
-};
-
-static struct ti_clk virt_13m_ck = {
- .name = "virt_13m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_13m_ck_data,
-};
-
-static struct ti_clk_fixed virt_19200000_ck_data = {
- .frequency = 19200000,
-};
-
-static struct ti_clk virt_19200000_ck = {
- .name = "virt_19200000_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_19200000_ck_data,
-};
-
-static struct ti_clk_fixed virt_26000000_ck_data = {
- .frequency = 26000000,
-};
-
-static struct ti_clk virt_26000000_ck = {
- .name = "virt_26000000_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_26000000_ck_data,
-};
-
-static struct ti_clk_fixed virt_38_4m_ck_data = {
- .frequency = 38400000,
-};
-
-static struct ti_clk virt_38_4m_ck = {
- .name = "virt_38_4m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_38_4m_ck_data,
-};
-
-static struct ti_clk_fixed virt_16_8m_ck_data = {
- .frequency = 16800000,
-};
-
-static struct ti_clk virt_16_8m_ck = {
- .name = "virt_16_8m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_16_8m_ck_data,
-};
-
-static const char *osc_sys_ck_parents[] = {
- "virt_12m_ck",
- "virt_13m_ck",
- "virt_19200000_ck",
- "virt_26000000_ck",
- "virt_38_4m_ck",
- "virt_16_8m_ck",
-};
-
-static struct ti_clk_mux osc_sys_ck_data = {
- .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_PRM,
- .parents = osc_sys_ck_parents,
-};
-
-static struct ti_clk osc_sys_ck = {
- .name = "osc_sys_ck",
- .type = TI_CLK_MUX,
- .data = &osc_sys_ck_data,
-};
-
-static struct ti_clk_divider sys_ck_data = {
- .parent = "osc_sys_ck",
- .bit_shift = 6,
- .max_div = 3,
- .reg = 0x1270,
- .module = TI_CLKM_PRM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk sys_ck = {
- .name = "sys_ck",
- .type = TI_CLK_DIVIDER,
- .data = &sys_ck_data,
-};
-
-static const char *dpll3_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll3_ck_data = {
- .num_parents = ARRAY_SIZE(dpll3_ck_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd40,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll3_ck_parents,
- .flags = CLKF_CORE,
- .freqsel_mask = 0xf0,
- .div1_mask = 0x7f00,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x5,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff0000,
- .recal_st_bit = 0x5,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll3_ck = {
- .name = "dpll3_ck",
- .clkdm_name = "dpll3_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll3_ck_data,
-};
-
-static struct ti_clk_divider dpll3_m2_ck_data = {
- .parent = "dpll3_ck",
- .bit_shift = 27,
- .max_div = 31,
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll3_m2_ck = {
- .name = "dpll3_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll3_m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor core_ck_data = {
- .parent = "dpll3_m2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_ck = {
- .name = "core_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_ck_data,
-};
-
-static struct ti_clk_divider l3_ick_data = {
- .parent = "core_ck",
- .max_div = 3,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk l3_ick = {
- .name = "l3_ick",
- .type = TI_CLK_DIVIDER,
- .data = &l3_ick_data,
-};
-
-static struct ti_clk_fixed_factor security_l3_ick_data = {
- .parent = "l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk security_l3_ick = {
- .name = "security_l3_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &security_l3_ick_data,
-};
-
-static struct ti_clk_fixed_factor wkup_l4_ick_data = {
- .parent = "sys_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wkup_l4_ick = {
- .name = "wkup_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wkup_l4_ick_data,
-};
-
-static struct ti_clk_gate usim_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 9,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk usim_ick = {
- .name = "usim_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &usim_ick_data,
-};
-
-static struct ti_clk_gate dss2_alwon_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 1,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk dss2_alwon_fck = {
- .name = "dss2_alwon_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss2_alwon_fck_data,
-};
-
-static struct ti_clk_divider l4_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 2,
- .max_div = 3,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk l4_ick = {
- .name = "l4_ick",
- .type = TI_CLK_DIVIDER,
- .data = &l4_ick_data,
-};
-
-static struct ti_clk_fixed_factor core_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_l4_ick = {
- .name = "core_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_l4_ick_data,
-};
-
-static struct ti_clk_gate mmchs2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 25,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs2_ick = {
- .name = "mmchs2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs2_ick_data,
-};
-
-static const char *dpll4_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll4_ck_data = {
- .num_parents = ARRAY_SIZE(dpll4_ck_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd44,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll4_ck_parents,
- .flags = CLKF_PER,
- .freqsel_mask = 0xf00000,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x2,
- .auto_recal_bit = 0x13,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x6,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x70000,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x6,
- .autoidle_mask = 0x38,
-};
-
-static struct ti_clk dpll4_ck = {
- .name = "dpll4_ck",
- .clkdm_name = "dpll4_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll4_ck_data,
-};
-
-static struct ti_clk_divider dpll4_m2_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 63,
- .reg = 0xd48,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m2_ck = {
- .name = "dpll4_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
- .parent = "dpll4_m2_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m2x2_mul_ck = {
- .name = "dpll4_m2x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m2x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m2x2_ck_data = {
- .parent = "dpll4_m2x2_mul_ck",
- .bit_shift = 0x1b,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m2x2_ck = {
- .name = "dpll4_m2x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m2x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
- .parent = "dpll4_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_alwon_fck = {
- .name = "omap_96m_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_alwon_fck_data,
-};
-
-static struct ti_clk_fixed_factor cm_96m_fck_data = {
- .parent = "omap_96m_alwon_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk cm_96m_fck = {
- .name = "cm_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &cm_96m_fck_data,
-};
-
-static const char *omap_96m_fck_parents[] = {
- "cm_96m_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux omap_96m_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_96m_fck_parents,
-};
-
-static struct ti_clk omap_96m_fck = {
- .name = "omap_96m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_96m_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_96m_fck_data = {
- .parent = "omap_96m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_96m_fck = {
- .name = "core_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_96m_fck_data,
-};
-
-static struct ti_clk_gate mspro_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 23,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mspro_fck = {
- .name = "mspro_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mspro_fck_data,
-};
-
-static struct ti_clk_gate dss_ick_3430es2_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0xe10,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk dss_ick_3430es2 = {
- .name = "dss_ick",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_ick_3430es2_data,
-};
-
-static struct ti_clk_gate uart4_ick_am35xx_data = {
- .parent = "core_l4_ick",
- .bit_shift = 23,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart4_ick_am35xx = {
- .name = "uart4_ick_am35xx",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_ick_am35xx_data,
-};
-
-static struct ti_clk_fixed_factor security_l4_ick2_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk security_l4_ick2 = {
- .name = "security_l4_ick2",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &security_l4_ick2_data,
-};
-
-static struct ti_clk_gate aes1_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 3,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk aes1_ick = {
- .name = "aes1_ick",
- .type = TI_CLK_GATE,
- .data = &aes1_ick_data,
-};
-
-static const char *dpll5_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll5_ck_data = {
- .num_parents = ARRAY_SIZE(dpll5_ck_parents),
- .control_reg = 0xd04,
- .idlest_reg = 0xd24,
- .mult_div1_reg = 0xd4c,
- .autoidle_reg = 0xd34,
- .module = TI_CLKM_CM,
- .parents = dpll5_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x19,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x19,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll5_ck = {
- .name = "dpll5_ck",
- .clkdm_name = "dpll5_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll5_ck_data,
-};
-
-static struct ti_clk_divider dpll5_m2_ck_data = {
- .parent = "dpll5_ck",
- .max_div = 31,
- .reg = 0xd50,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll5_m2_ck = {
- .name = "dpll5_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll5_m2_ck_data,
-};
-
-static struct ti_clk_gate usbhost_120m_fck_data = {
- .parent = "dpll5_m2_ck",
- .bit_shift = 1,
- .reg = 0x1400,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk usbhost_120m_fck = {
- .name = "usbhost_120m_fck",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_120m_fck_data,
-};
-
-static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
- .parent = "cm_96m_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk cm_96m_d2_fck = {
- .name = "cm_96m_d2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &cm_96m_d2_fck_data,
-};
-
-static struct ti_clk_fixed sys_altclk_data = {
- .frequency = 0x0,
-};
-
-static struct ti_clk sys_altclk = {
- .name = "sys_altclk",
- .type = TI_CLK_FIXED,
- .data = &sys_altclk_data,
-};
-
-static const char *omap_48m_fck_parents[] = {
- "cm_96m_d2_fck",
- "sys_altclk",
-};
-
-static struct ti_clk_mux omap_48m_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_48m_fck_parents,
-};
-
-static struct ti_clk omap_48m_fck = {
- .name = "omap_48m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_48m_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_48m_fck_data = {
- .parent = "omap_48m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_48m_fck = {
- .name = "core_48m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_48m_fck_data,
-};
-
-static struct ti_clk_fixed mcbsp_clks_data = {
- .frequency = 0x0,
-};
-
-static struct ti_clk mcbsp_clks = {
- .name = "mcbsp_clks",
- .type = TI_CLK_FIXED,
- .data = &mcbsp_clks_data,
-};
-
-static struct ti_clk_gate mcbsp2_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 0,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor per_96m_fck_data = {
- .parent = "omap_96m_alwon_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_96m_fck = {
- .name = "per_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_96m_fck_data,
-};
-
-static const char *mcbsp2_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp2_mux_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
- .reg = 0x274,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp2_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp2_fck_data = {
- .mux = &mcbsp2_mux_fck_data,
- .gate = &mcbsp2_gate_fck_data,
-};
-
-static struct ti_clk mcbsp2_fck = {
- .name = "mcbsp2_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp2_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
- .parent = "dpll3_m2_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll3_m2x2_ck = {
- .name = "dpll3_m2x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll3_m2x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_fck_data = {
- .parent = "dpll3_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk corex2_fck = {
- .name = "corex2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_fck_data,
-};
-
-static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
- .parent = "corex2_fck",
- .bit_shift = 0,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static int ssi_ssr_div_fck_3430es1_divs[] = {
- 0,
- 1,
- 2,
- 3,
- 4,
- 0,
- 6,
- 0,
- 8,
-};
-
-static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
- .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
- .parent = "corex2_fck",
- .bit_shift = 8,
- .dividers = ssi_ssr_div_fck_3430es1_divs,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
- .gate = &ssi_ssr_gate_fck_3430es1_data,
- .divider = &ssi_ssr_div_fck_3430es1_data,
-};
-
-static struct ti_clk ssi_ssr_fck_3430es1 = {
- .name = "ssi_ssr_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &ssi_ssr_fck_3430es1_data,
-};
-
-static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
- .parent = "ssi_ssr_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk ssi_sst_fck_3430es1 = {
- .name = "ssi_sst_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &ssi_sst_fck_3430es1_data,
-};
-
-static struct ti_clk_fixed omap_32k_fck_data = {
- .frequency = 32768,
-};
-
-static struct ti_clk omap_32k_fck = {
- .name = "omap_32k_fck",
- .type = TI_CLK_FIXED,
- .data = &omap_32k_fck_data,
-};
-
-static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
- .parent = "omap_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_32k_alwon_fck = {
- .name = "per_32k_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_32k_alwon_fck_data,
-};
-
-static struct ti_clk_gate gpio5_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 16,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio5_dbck = {
- .name = "gpio5_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio5_dbck_data,
-};
-
-static struct ti_clk_gate gpt1_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 0,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt1_ick = {
- .name = "gpt1_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt1_ick_data,
-};
-
-static struct ti_clk_gate mcspi3_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 20,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi3_fck = {
- .name = "mcspi3_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi3_fck_data,
-};
-
-static struct ti_clk_gate gpt2_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 3,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt2_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt2_mux_fck_data = {
- .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt2_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt2_fck_data = {
- .mux = &gpt2_mux_fck_data,
- .gate = &gpt2_gate_fck_data,
-};
-
-static struct ti_clk gpt2_fck = {
- .name = "gpt2_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt2_fck_data,
-};
-
-static struct ti_clk_gate gpt10_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 11,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt10_ick = {
- .name = "gpt10_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt10_ick_data,
-};
-
-static struct ti_clk_gate uart2_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 14,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart2_fck = {
- .name = "uart2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart2_fck_data,
-};
-
-static struct ti_clk_fixed_factor sr_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk sr_l4_ick = {
- .name = "sr_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &sr_l4_ick_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
- .parent = "omap_96m_fck",
- .div = 8,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d8_fck = {
- .name = "omap_96m_d8_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d8_fck_data,
-};
-
-static struct ti_clk_divider dpll4_m5_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 63,
- .reg = 0xf40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m5_ck = {
- .name = "dpll4_m5_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m5_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
- .parent = "dpll4_m5_ck",
- .div = 1,
- .mult = 2,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dpll4_m5x2_mul_ck = {
- .name = "dpll4_m5x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m5x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m5x2_ck_data = {
- .parent = "dpll4_m5x2_mul_ck",
- .bit_shift = 0x1e,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m5x2_ck = {
- .name = "dpll4_m5x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m5x2_ck_data,
-};
-
-static struct ti_clk_gate cam_mclk_data = {
- .parent = "dpll4_m5x2_ck",
- .bit_shift = 0,
- .reg = 0xf00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk cam_mclk = {
- .name = "cam_mclk",
- .type = TI_CLK_GATE,
- .data = &cam_mclk_data,
-};
-
-static struct ti_clk_gate mcbsp3_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 1,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *mcbsp3_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp3_mux_fck_data = {
- .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp3_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp3_fck_data = {
- .mux = &mcbsp3_mux_fck_data,
- .gate = &mcbsp3_gate_fck_data,
-};
-
-static struct ti_clk mcbsp3_fck = {
- .name = "mcbsp3_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp3_fck_data,
-};
-
-static struct ti_clk_gate csi2_96m_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 1,
- .reg = 0xf00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk csi2_96m_fck = {
- .name = "csi2_96m_fck",
- .clkdm_name = "cam_clkdm",
- .type = TI_CLK_GATE,
- .data = &csi2_96m_fck_data,
-};
-
-static struct ti_clk_gate gpt9_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 10,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt9_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt9_mux_fck_data = {
- .bit_shift = 7,
- .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt9_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt9_fck_data = {
- .mux = &gpt9_mux_fck_data,
- .gate = &gpt9_gate_fck_data,
-};
-
-static struct ti_clk gpt9_fck = {
- .name = "gpt9_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt9_fck_data,
-};
-
-static struct ti_clk_divider dpll3_m3_ck_data = {
- .parent = "dpll3_ck",
- .bit_shift = 16,
- .max_div = 31,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll3_m3_ck = {
- .name = "dpll3_m3_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll3_m3_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
- .parent = "dpll3_m3_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll3_m3x2_mul_ck = {
- .name = "dpll3_m3x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll3_m3x2_mul_ck_data,
-};
-
-static struct ti_clk_gate sr2_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 7,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk sr2_fck = {
- .name = "sr2_fck",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &sr2_fck_data,
-};
-
-static struct ti_clk_fixed pclk_ck_data = {
- .frequency = 27000000,
-};
-
-static struct ti_clk pclk_ck = {
- .name = "pclk_ck",
- .type = TI_CLK_FIXED,
- .data = &pclk_ck_data,
-};
-
-static struct ti_clk_gate wdt2_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 5,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk wdt2_ick = {
- .name = "wdt2_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt2_ick_data,
-};
-
-static struct ti_clk_fixed_factor core_l3_ick_data = {
- .parent = "l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_l3_ick = {
- .name = "core_l3_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_l3_ick_data,
-};
-
-static struct ti_clk_gate mcspi4_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 21,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi4_fck = {
- .name = "mcspi4_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi4_fck_data,
-};
-
-static struct ti_clk_fixed_factor per_48m_fck_data = {
- .parent = "omap_48m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_48m_fck = {
- .name = "per_48m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_48m_fck_data,
-};
-
-static struct ti_clk_gate uart4_fck_data = {
- .parent = "per_48m_fck",
- .bit_shift = 18,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart4_fck = {
- .name = "uart4_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_fck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
- .parent = "omap_96m_fck",
- .div = 10,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d10_fck = {
- .name = "omap_96m_d10_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d10_fck_data,
-};
-
-static struct ti_clk_gate usim_gate_fck_data = {
- .parent = "omap_96m_fck",
- .bit_shift = 9,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor per_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_l4_ick = {
- .name = "per_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_l4_ick_data,
-};
-
-static struct ti_clk_gate gpt5_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 6,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt5_ick = {
- .name = "gpt5_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt5_ick_data,
-};
-
-static struct ti_clk_gate mcspi2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 19,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcspi2_ick = {
- .name = "mcspi2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi2_ick_data,
-};
-
-static struct ti_clk_fixed_factor ssi_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk ssi_l4_ick = {
- .name = "ssi_l4_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &ssi_l4_ick_data,
-};
-
-static struct ti_clk_gate ssi_ick_3430es1_data = {
- .parent = "ssi_l4_ick",
- .bit_shift = 0,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk ssi_ick_3430es1 = {
- .name = "ssi_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &ssi_ick_3430es1_data,
-};
-
-static struct ti_clk_gate i2c2_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 16,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk i2c2_fck = {
- .name = "i2c2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c2_fck_data,
-};
-
-static struct ti_clk_divider dpll1_fck_data = {
- .parent = "core_ck",
- .bit_shift = 19,
- .max_div = 7,
- .reg = 0x940,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll1_fck = {
- .name = "dpll1_fck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll1_fck_data,
-};
-
-static const char *dpll1_ck_parents[] = {
- "sys_ck",
- "dpll1_fck",
-};
-
-static struct ti_clk_dpll dpll1_ck_data = {
- .num_parents = ARRAY_SIZE(dpll1_ck_parents),
- .control_reg = 0x904,
- .idlest_reg = 0x924,
- .mult_div1_reg = 0x940,
- .autoidle_reg = 0x934,
- .module = TI_CLKM_CM,
- .parents = dpll1_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0xa0,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x7,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x7,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll1_ck = {
- .name = "dpll1_ck",
- .clkdm_name = "dpll1_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll1_ck_data,
-};
-
-static struct ti_clk_fixed secure_32k_fck_data = {
- .frequency = 32768,
-};
-
-static struct ti_clk secure_32k_fck = {
- .name = "secure_32k_fck",
- .type = TI_CLK_FIXED,
- .data = &secure_32k_fck_data,
-};
-
-static struct ti_clk_gate gpio5_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 16,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio5_ick = {
- .name = "gpio5_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio5_ick_data,
-};
-
-static struct ti_clk_divider dpll4_m4_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 32,
- .reg = 0xe40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m4_ck = {
- .name = "dpll4_m4_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m4_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
- .parent = "dpll4_m4_ck",
- .div = 1,
- .mult = 2,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dpll4_m4x2_mul_ck = {
- .name = "dpll4_m4x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m4x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m4x2_ck_data = {
- .parent = "dpll4_m4x2_mul_ck",
- .bit_shift = 0x1d,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m4x2_ck = {
- .name = "dpll4_m4x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m4x2_ck_data,
-};
-
-static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
- .parent = "dpll4_m4x2_ck",
- .bit_shift = 0,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dss1_alwon_fck_3430es2 = {
- .name = "dss1_alwon_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss1_alwon_fck_3430es2_data,
-};
-
-static struct ti_clk_gate uart3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 11,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart3_ick = {
- .name = "uart3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart3_ick_data,
-};
-
-static struct ti_clk_divider dpll4_m3_ck_data = {
- .parent = "dpll4_ck",
- .bit_shift = 8,
- .max_div = 32,
- .reg = 0xe40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m3_ck = {
- .name = "dpll4_m3_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m3_ck_data,
-};
-
-static struct ti_clk_gate mcbsp3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 1,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp3_ick = {
- .name = "mcbsp3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp3_ick_data,
-};
-
-static struct ti_clk_gate gpio3_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 14,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio3_dbck = {
- .name = "gpio3_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio3_dbck_data,
-};
-
-static struct ti_clk_gate fac_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 8,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk fac_ick = {
- .name = "fac_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &fac_ick_data,
-};
-
-static struct ti_clk_gate clkout2_src_gate_ck_data = {
- .parent = "core_ck",
- .bit_shift = 7,
- .reg = 0xd70,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
- .parent = "dpll4_m3_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m3x2_mul_ck = {
- .name = "dpll4_m3x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m3x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m3x2_ck_data = {
- .parent = "dpll4_m3x2_mul_ck",
- .bit_shift = 0x1c,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m3x2_ck = {
- .name = "dpll4_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m3x2_ck_data,
-};
-
-static const char *omap_54m_fck_parents[] = {
- "dpll4_m3x2_ck",
- "sys_altclk",
-};
-
-static struct ti_clk_mux omap_54m_fck_data = {
- .bit_shift = 5,
- .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_54m_fck_parents,
-};
-
-static struct ti_clk omap_54m_fck = {
- .name = "omap_54m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_54m_fck_data,
-};
-
-static const char *clkout2_src_mux_ck_parents[] = {
- "core_ck",
- "sys_ck",
- "cm_96m_fck",
- "omap_54m_fck",
-};
-
-static struct ti_clk_mux clkout2_src_mux_ck_data = {
- .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
- .reg = 0xd70,
- .module = TI_CLKM_CM,
- .parents = clkout2_src_mux_ck_parents,
-};
-
-static struct ti_clk_composite clkout2_src_ck_data = {
- .mux = &clkout2_src_mux_ck_data,
- .gate = &clkout2_src_gate_ck_data,
-};
-
-static struct ti_clk clkout2_src_ck = {
- .name = "clkout2_src_ck",
- .type = TI_CLK_COMPOSITE,
- .data = &clkout2_src_ck_data,
-};
-
-static struct ti_clk_gate i2c1_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 15,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk i2c1_fck = {
- .name = "i2c1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c1_fck_data,
-};
-
-static struct ti_clk_gate wdt3_fck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 12,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk wdt3_fck = {
- .name = "wdt3_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt3_fck_data,
-};
-
-static struct ti_clk_gate gpt7_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 8,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt7_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt7_mux_fck_data = {
- .bit_shift = 5,
- .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt7_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt7_fck_data = {
- .mux = &gpt7_mux_fck_data,
- .gate = &gpt7_gate_fck_data,
-};
-
-static struct ti_clk gpt7_fck = {
- .name = "gpt7_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt7_fck_data,
-};
-
-static struct ti_clk_gate usb_l4_gate_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 5,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_INTERFACE,
-};
-
-static struct ti_clk_divider usb_l4_div_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 4,
- .max_div = 1,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk_composite usb_l4_ick_data = {
- .gate = &usb_l4_gate_ick_data,
- .divider = &usb_l4_div_ick_data,
-};
-
-static struct ti_clk usb_l4_ick = {
- .name = "usb_l4_ick",
- .type = TI_CLK_COMPOSITE,
- .data = &usb_l4_ick_data,
-};
-
-static struct ti_clk_gate uart4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 18,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart4_ick = {
- .name = "uart4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_ick_data,
-};
-
-static struct ti_clk_fixed dummy_ck_data = {
- .frequency = 0,
-};
-
-static struct ti_clk dummy_ck = {
- .name = "dummy_ck",
- .type = TI_CLK_FIXED,
- .data = &dummy_ck_data,
-};
-
-static const char *gpt3_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt3_mux_fck_data = {
- .bit_shift = 1,
- .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt3_mux_fck_parents,
-};
-
-static struct ti_clk_gate gpt9_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 10,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt9_ick = {
- .name = "gpt9_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt9_ick_data,
-};
-
-static struct ti_clk_gate gpt10_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 11,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate dss_ick_3430es1_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0xe10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk dss_ick_3430es1 = {
- .name = "dss_ick",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_ick_3430es1_data,
-};
-
-static struct ti_clk_gate gpt11_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 12,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt11_ick = {
- .name = "gpt11_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt11_ick_data,
-};
-
-static struct ti_clk_divider dpll2_fck_data = {
- .parent = "core_ck",
- .bit_shift = 19,
- .max_div = 7,
- .reg = 0x40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll2_fck = {
- .name = "dpll2_fck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll2_fck_data,
-};
-
-static struct ti_clk_gate uart1_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 13,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart1_fck = {
- .name = "uart1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart1_fck_data,
-};
-
-static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
- .parent = "core_l3_ick",
- .bit_shift = 4,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk hsotgusb_ick_3430es1 = {
- .name = "hsotgusb_ick_3430es1",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_ick_3430es1_data,
-};
-
-static struct ti_clk_gate gpio2_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 13,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio2_ick = {
- .name = "gpio2_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio2_ick_data,
-};
-
-static struct ti_clk_gate mmchs1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 24,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs1_ick = {
- .name = "mmchs1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs1_ick_data,
-};
-
-static struct ti_clk_gate modem_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 31,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk modem_fck = {
- .name = "modem_fck",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &modem_fck_data,
-};
-
-static struct ti_clk_gate mcbsp4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 2,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp4_ick = {
- .name = "mcbsp4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp4_ick_data,
-};
-
-static struct ti_clk_gate gpio1_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 3,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio1_ick = {
- .name = "gpio1_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio1_ick_data,
-};
-
-static const char *gpt6_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt6_mux_fck_data = {
- .bit_shift = 4,
- .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt6_mux_fck_parents,
-};
-
-static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
- .parent = "dpll1_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll1_x2_ck = {
- .name = "dpll1_x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll1_x2_ck_data,
-};
-
-static struct ti_clk_divider dpll1_x2m2_ck_data = {
- .parent = "dpll1_x2_ck",
- .max_div = 31,
- .reg = 0x944,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll1_x2m2_ck = {
- .name = "dpll1_x2m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll1_x2m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor mpu_ck_data = {
- .parent = "dpll1_x2m2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk mpu_ck = {
- .name = "mpu_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &mpu_ck_data,
-};
-
-static struct ti_clk_divider arm_fck_data = {
- .parent = "mpu_ck",
- .max_div = 2,
- .reg = 0x924,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk arm_fck = {
- .name = "arm_fck",
- .type = TI_CLK_DIVIDER,
- .data = &arm_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d3_ck_data = {
- .parent = "core_ck",
- .div = 3,
- .mult = 1,
-};
-
-static struct ti_clk core_d3_ck = {
- .name = "core_d3_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d3_ck_data,
-};
-
-static struct ti_clk_gate gpt11_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 12,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt11_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt11_mux_fck_data = {
- .bit_shift = 7,
- .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .parents = gpt11_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt11_fck_data = {
- .mux = &gpt11_mux_fck_data,
- .gate = &gpt11_gate_fck_data,
-};
-
-static struct ti_clk gpt11_fck = {
- .name = "gpt11_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt11_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d6_ck_data = {
- .parent = "core_ck",
- .div = 6,
- .mult = 1,
-};
-
-static struct ti_clk core_d6_ck = {
- .name = "core_d6_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d6_ck_data,
-};
-
-static struct ti_clk_gate uart4_fck_am35xx_data = {
- .parent = "core_48m_fck",
- .bit_shift = 23,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart4_fck_am35xx = {
- .name = "uart4_fck_am35xx",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_fck_am35xx_data,
-};
-
-static struct ti_clk_gate dpll3_m3x2_ck_data = {
- .parent = "dpll3_m3x2_mul_ck",
- .bit_shift = 0xc,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll3_m3x2_ck = {
- .name = "dpll3_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll3_m3x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
- .parent = "dpll3_m3x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_core_alwon_ck = {
- .name = "emu_core_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_core_alwon_ck_data,
-};
-
-static struct ti_clk_divider dpll4_m6_ck_data = {
- .parent = "dpll4_ck",
- .bit_shift = 24,
- .max_div = 63,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m6_ck = {
- .name = "dpll4_m6_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m6_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
- .parent = "dpll4_m6_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m6x2_mul_ck = {
- .name = "dpll4_m6x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m6x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m6x2_ck_data = {
- .parent = "dpll4_m6x2_mul_ck",
- .bit_shift = 0x1f,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m6x2_ck = {
- .name = "dpll4_m6x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m6x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
- .parent = "dpll4_m6x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_per_alwon_ck = {
- .name = "emu_per_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_per_alwon_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
- .parent = "mpu_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_mpu_alwon_ck = {
- .name = "emu_mpu_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_mpu_alwon_ck_data,
-};
-
-static const char *emu_src_mux_ck_parents[] = {
- "sys_ck",
- "emu_core_alwon_ck",
- "emu_per_alwon_ck",
- "emu_mpu_alwon_ck",
-};
-
-static struct ti_clk_mux emu_src_mux_ck_data = {
- .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .parents = emu_src_mux_ck_parents,
-};
-
-static struct ti_clk emu_src_mux_ck = {
- .name = "emu_src_mux_ck",
- .type = TI_CLK_MUX,
- .data = &emu_src_mux_ck_data,
-};
-
-static struct ti_clk_gate emu_src_ck_data = {
- .parent = "emu_src_mux_ck",
- .flags = CLKF_CLKDM,
-};
-
-static struct ti_clk emu_src_ck = {
- .name = "emu_src_ck",
- .clkdm_name = "emu_clkdm",
- .type = TI_CLK_GATE,
- .data = &emu_src_ck_data,
-};
-
-static struct ti_clk_divider atclk_fck_data = {
- .parent = "emu_src_ck",
- .bit_shift = 4,
- .max_div = 3,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk atclk_fck = {
- .name = "atclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &atclk_fck_data,
-};
-
-static struct ti_clk_gate ipss_ick_data = {
- .parent = "core_l3_ick",
- .bit_shift = 4,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_AM35XX | CLKF_INTERFACE,
-};
-
-static struct ti_clk ipss_ick = {
- .name = "ipss_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &ipss_ick_data,
-};
-
-static struct ti_clk_gate emac_ick_data = {
- .parent = "ipss_ick",
- .bit_shift = 1,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk emac_ick = {
- .name = "emac_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &emac_ick_data,
-};
-
-static struct ti_clk_gate vpfe_ick_data = {
- .parent = "ipss_ick",
- .bit_shift = 2,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk vpfe_ick = {
- .name = "vpfe_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &vpfe_ick_data,
-};
-
-static const char *dpll2_ck_parents[] = {
- "sys_ck",
- "dpll2_fck",
-};
-
-static struct ti_clk_dpll dpll2_ck_data = {
- .num_parents = ARRAY_SIZE(dpll2_ck_parents),
- .control_reg = 0x4,
- .idlest_reg = 0x24,
- .mult_div1_reg = 0x40,
- .autoidle_reg = 0x34,
- .module = TI_CLKM_CM,
- .parents = dpll2_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0xa2,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x8,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x8,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll2_ck = {
- .name = "dpll2_ck",
- .clkdm_name = "dpll2_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll2_ck_data,
-};
-
-static struct ti_clk_divider dpll2_m2_ck_data = {
- .parent = "dpll2_ck",
- .max_div = 31,
- .reg = 0x44,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll2_m2_ck = {
- .name = "dpll2_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll2_m2_ck_data,
-};
-
-static const char *mcbsp4_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp4_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp4_mux_fck_parents,
-};
-
-static const char *mcbsp1_mux_fck_parents[] = {
- "core_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp1_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
- .reg = 0x274,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp1_mux_fck_parents,
-};
-
-static struct ti_clk_gate gpt8_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 9,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate gpt8_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 9,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt8_ick = {
- .name = "gpt8_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt8_ick_data,
-};
-
-static const char *gpt10_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt10_mux_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .parents = gpt10_mux_fck_parents,
-};
-
-static struct ti_clk_gate mmchs3_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 30,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs3_ick = {
- .name = "mmchs3_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs3_ick_data,
-};
-
-static struct ti_clk_gate gpio3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 14,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio3_ick = {
- .name = "gpio3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio3_ick_data,
-};
-
-static const char *traceclk_src_fck_parents[] = {
- "sys_ck",
- "emu_core_alwon_ck",
- "emu_per_alwon_ck",
- "emu_mpu_alwon_ck",
-};
-
-static struct ti_clk_mux traceclk_src_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .parents = traceclk_src_fck_parents,
-};
-
-static struct ti_clk traceclk_src_fck = {
- .name = "traceclk_src_fck",
- .type = TI_CLK_MUX,
- .data = &traceclk_src_fck_data,
-};
-
-static struct ti_clk_divider traceclk_fck_data = {
- .parent = "traceclk_src_fck",
- .bit_shift = 11,
- .max_div = 7,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk traceclk_fck = {
- .name = "traceclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &traceclk_fck_data,
-};
-
-static struct ti_clk_gate mcbsp5_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 10,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate sad2d_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 3,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk sad2d_ick = {
- .name = "sad2d_ick",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &sad2d_ick_data,
-};
-
-static const char *gpt1_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt1_mux_fck_data = {
- .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
- .reg = 0xc40,
- .module = TI_CLKM_CM,
- .parents = gpt1_mux_fck_parents,
-};
-
-static struct ti_clk_gate hecc_ck_data = {
- .parent = "sys_ck",
- .bit_shift = 3,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk hecc_ck = {
- .name = "hecc_ck",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hecc_ck_data,
-};
-
-static struct ti_clk_gate gpt1_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 0,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite gpt1_fck_data = {
- .mux = &gpt1_mux_fck_data,
- .gate = &gpt1_gate_fck_data,
-};
-
-static struct ti_clk gpt1_fck = {
- .name = "gpt1_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt1_fck_data,
-};
-
-static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
- .parent = "dpll4_m2x2_mul_ck",
- .bit_shift = 0x1b,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m2x2_ck_omap36xx = {
- .name = "dpll4_m2x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m2x2_ck_omap36xx_data,
- .patch = &dpll4_m2x2_ck,
-};
-
-static struct ti_clk_divider gfx_l3_fck_data = {
- .parent = "l3_ick",
- .max_div = 7,
- .reg = 0xb40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk gfx_l3_fck = {
- .name = "gfx_l3_fck",
- .type = TI_CLK_DIVIDER,
- .data = &gfx_l3_fck_data,
-};
-
-static struct ti_clk_gate gfx_cg1_ck_data = {
- .parent = "gfx_l3_fck",
- .bit_shift = 1,
- .reg = 0xb00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk gfx_cg1_ck = {
- .name = "gfx_cg1_ck",
- .clkdm_name = "gfx_3430es1_clkdm",
- .type = TI_CLK_GATE,
- .data = &gfx_cg1_ck_data,
-};
-
-static struct ti_clk_gate mailboxes_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 7,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mailboxes_ick = {
- .name = "mailboxes_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mailboxes_ick_data,
-};
-
-static struct ti_clk_gate sha11_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 1,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk sha11_ick = {
- .name = "sha11_ick",
- .type = TI_CLK_GATE,
- .data = &sha11_ick_data,
-};
-
-static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
- .parent = "ipss_ick",
- .bit_shift = 0,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk hsotgusb_ick_am35xx = {
- .name = "hsotgusb_ick_am35xx",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_ick_am35xx_data,
-};
-
-static struct ti_clk_gate mmchs3_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 30,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mmchs3_fck = {
- .name = "mmchs3_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs3_fck_data,
-};
-
-static struct ti_clk_divider pclk_fck_data = {
- .parent = "emu_src_ck",
- .bit_shift = 8,
- .max_div = 7,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk pclk_fck = {
- .name = "pclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &pclk_fck_data,
-};
-
-static const char *dpll4_ck_omap36xx_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
- .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd44,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll4_ck_omap36xx_parents,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x2,
- .auto_recal_bit = 0x13,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x6,
- .max_multiplier = 0xfff,
- .enable_mask = 0x70000,
- .mult_mask = 0xfff00,
- .recal_st_bit = 0x6,
- .autoidle_mask = 0x38,
- .sddiv_mask = 0xff000000,
- .dco_mask = 0xe00000,
- .flags = CLKF_PER | CLKF_J_TYPE,
-};
-
-static struct ti_clk dpll4_ck_omap36xx = {
- .name = "dpll4_ck",
- .type = TI_CLK_DPLL,
- .data = &dpll4_ck_omap36xx_data,
- .patch = &dpll4_ck,
-};
-
-static struct ti_clk_gate uart3_fck_data = {
- .parent = "per_48m_fck",
- .bit_shift = 11,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart3_fck = {
- .name = "uart3_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart3_fck_data,
-};
-
-static struct ti_clk_fixed_factor wkup_32k_fck_data = {
- .parent = "omap_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wkup_32k_fck = {
- .name = "wkup_32k_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wkup_32k_fck_data,
-};
-
-static struct ti_clk_gate sys_clkout1_data = {
- .parent = "osc_sys_ck",
- .bit_shift = 7,
- .reg = 0xd70,
- .module = TI_CLKM_PRM,
-};
-
-static struct ti_clk sys_clkout1 = {
- .name = "sys_clkout1",
- .type = TI_CLK_GATE,
- .data = &sys_clkout1_data,
-};
-
-static struct ti_clk_fixed_factor gpmc_fck_data = {
- .parent = "core_l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk gpmc_fck = {
- .name = "gpmc_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &gpmc_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 20,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d20_ck = {
- .name = "dpll5_m2_d20_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d20_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
- .parent = "dpll4_m5x2_mul_ck",
- .bit_shift = 0x1e,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m5x2_ck_omap36xx = {
- .name = "dpll4_m5x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m5x2_ck_omap36xx_data,
- .patch = &dpll4_m5x2_ck,
-};
-
-static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
- .parent = "corex2_fck",
- .bit_shift = 0,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static struct ti_clk_gate uart1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 13,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart1_ick = {
- .name = "uart1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart1_ick_data,
-};
-
-static struct ti_clk_gate iva2_ck_data = {
- .parent = "dpll2_m2_ck",
- .bit_shift = 0,
- .reg = 0x0,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk iva2_ck = {
- .name = "iva2_ck",
- .clkdm_name = "iva2_clkdm",
- .type = TI_CLK_GATE,
- .data = &iva2_ck_data,
-};
-
-static struct ti_clk_gate pka_ick_data = {
- .parent = "security_l3_ick",
- .bit_shift = 4,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk pka_ick = {
- .name = "pka_ick",
- .type = TI_CLK_GATE,
- .data = &pka_ick_data,
-};
-
-static struct ti_clk_gate gpt12_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 1,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt12_ick = {
- .name = "gpt12_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt12_ick_data,
-};
-
-static const char *mcbsp5_mux_fck_parents[] = {
- "core_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp5_mux_fck_data = {
- .bit_shift = 4,
- .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp5_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp5_fck_data = {
- .mux = &mcbsp5_mux_fck_data,
- .gate = &mcbsp5_gate_fck_data,
-};
-
-static struct ti_clk mcbsp5_fck = {
- .name = "mcbsp5_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp5_fck_data,
-};
-
-static struct ti_clk_gate usbhost_48m_fck_data = {
- .parent = "omap_48m_fck",
- .bit_shift = 0,
- .reg = 0x1400,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS,
-};
-
-static struct ti_clk usbhost_48m_fck = {
- .name = "usbhost_48m_fck",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_48m_fck_data,
-};
-
-static struct ti_clk_gate des1_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 0,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk des1_ick = {
- .name = "des1_ick",
- .type = TI_CLK_GATE,
- .data = &des1_ick_data,
-};
-
-static struct ti_clk_gate sgx_gate_fck_data = {
- .parent = "core_ck",
- .bit_shift = 1,
- .reg = 0xb00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor core_d4_ck_data = {
- .parent = "core_ck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk core_d4_ck = {
- .name = "core_d4_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d4_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
- .parent = "dpll4_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk omap_192m_alwon_fck = {
- .name = "omap_192m_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_192m_alwon_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d2_ck_data = {
- .parent = "core_ck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk core_d2_ck = {
- .name = "core_d2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d2_ck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_d3_fck_data = {
- .parent = "corex2_fck",
- .div = 3,
- .mult = 1,
-};
-
-static struct ti_clk corex2_d3_fck = {
- .name = "corex2_d3_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_d3_fck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_d5_fck_data = {
- .parent = "corex2_fck",
- .div = 5,
- .mult = 1,
-};
-
-static struct ti_clk corex2_d5_fck = {
- .name = "corex2_d5_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_d5_fck_data,
-};
-
-static const char *sgx_mux_fck_parents[] = {
- "core_d3_ck",
- "core_d4_ck",
- "core_d6_ck",
- "cm_96m_fck",
- "omap_192m_alwon_fck",
- "core_d2_ck",
- "corex2_d3_fck",
- "corex2_d5_fck",
-};
-
-static struct ti_clk_mux sgx_mux_fck_data = {
- .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
- .reg = 0xb40,
- .module = TI_CLKM_CM,
- .parents = sgx_mux_fck_parents,
-};
-
-static struct ti_clk_composite sgx_fck_data = {
- .mux = &sgx_mux_fck_data,
- .gate = &sgx_gate_fck_data,
-};
-
-static struct ti_clk sgx_fck = {
- .name = "sgx_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &sgx_fck_data,
-};
-
-static struct ti_clk_gate mcspi1_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 18,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi1_fck = {
- .name = "mcspi1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi1_fck_data,
-};
-
-static struct ti_clk_gate mmchs2_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 25,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mmchs2_fck = {
- .name = "mmchs2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs2_fck_data,
-};
-
-static struct ti_clk_gate mcspi2_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 19,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi2_fck = {
- .name = "mcspi2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi2_fck_data,
-};
-
-static struct ti_clk_gate vpfe_fck_data = {
- .parent = "pclk_ck",
- .bit_shift = 10,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
-};
-
-static struct ti_clk vpfe_fck = {
- .name = "vpfe_fck",
- .type = TI_CLK_GATE,
- .data = &vpfe_fck_data,
-};
-
-static struct ti_clk_gate gpt4_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 5,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate mcbsp1_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 9,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate gpt5_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 6,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt5_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt5_mux_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt5_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt5_fck_data = {
- .mux = &gpt5_mux_fck_data,
- .gate = &gpt5_gate_fck_data,
-};
-
-static struct ti_clk gpt5_fck = {
- .name = "gpt5_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt5_fck_data,
-};
-
-static struct ti_clk_gate ts_fck_data = {
- .parent = "omap_32k_fck",
- .bit_shift = 1,
- .reg = 0xa08,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk ts_fck = {
- .name = "ts_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &ts_fck_data,
-};
-
-static struct ti_clk_fixed_factor wdt1_fck_data = {
- .parent = "secure_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wdt1_fck = {
- .name = "wdt1_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wdt1_fck_data,
-};
-
-static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
- .parent = "dpll4_m6x2_mul_ck",
- .bit_shift = 0x1f,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m6x2_ck_omap36xx = {
- .name = "dpll4_m6x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m6x2_ck_omap36xx_data,
- .patch = &dpll4_m6x2_ck,
-};
-
-static const char *gpt4_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt4_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt4_mux_fck_parents,
-};
-
-static struct ti_clk_gate usbhost_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0x1410,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk usbhost_ick = {
- .name = "usbhost_ick",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_ick_data,
-};
-
-static struct ti_clk_gate mcbsp2_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 0,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp2_ick = {
- .name = "mcbsp2_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp2_ick_data,
-};
-
-static struct ti_clk_gate omapctrl_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 6,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk omapctrl_ick = {
- .name = "omapctrl_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &omapctrl_ick_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
- .parent = "omap_96m_fck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d4_fck = {
- .name = "omap_96m_d4_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d4_fck_data,
-};
-
-static struct ti_clk_gate gpt6_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 7,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt6_ick = {
- .name = "gpt6_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt6_ick_data,
-};
-
-static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
- .parent = "dpll3_m3x2_mul_ck",
- .bit_shift = 0xc,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll3_m3x2_ck_omap36xx = {
- .name = "dpll3_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll3_m3x2_ck_omap36xx_data,
- .patch = &dpll3_m3x2_ck,
-};
-
-static struct ti_clk_gate i2c3_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 17,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk i2c3_ick = {
- .name = "i2c3_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c3_ick_data,
-};
-
-static struct ti_clk_gate gpio6_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 17,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio6_ick = {
- .name = "gpio6_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio6_ick_data,
-};
-
-static struct ti_clk_gate mspro_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 23,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mspro_ick = {
- .name = "mspro_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mspro_ick_data,
-};
-
-static struct ti_clk_composite mcbsp1_fck_data = {
- .mux = &mcbsp1_mux_fck_data,
- .gate = &mcbsp1_gate_fck_data,
-};
-
-static struct ti_clk mcbsp1_fck = {
- .name = "mcbsp1_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp1_fck_data,
-};
-
-static struct ti_clk_gate gpt3_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 4,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed rmii_ck_data = {
- .frequency = 50000000,
-};
-
-static struct ti_clk rmii_ck = {
- .name = "rmii_ck",
- .type = TI_CLK_FIXED,
- .data = &rmii_ck_data,
-};
-
-static struct ti_clk_gate gpt6_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 7,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite gpt6_fck_data = {
- .mux = &gpt6_mux_fck_data,
- .gate = &gpt6_gate_fck_data,
-};
-
-static struct ti_clk gpt6_fck = {
- .name = "gpt6_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt6_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d4_ck = {
- .name = "dpll5_m2_d4_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d4_ck_data,
-};
-
-static struct ti_clk_fixed_factor sys_d2_ck_data = {
- .parent = "sys_ck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk sys_d2_ck = {
- .name = "sys_d2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &sys_d2_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
- .parent = "omap_96m_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d2_fck = {
- .name = "omap_96m_d2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d2_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 8,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d8_ck = {
- .name = "dpll5_m2_d8_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d8_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 16,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d16_ck = {
- .name = "dpll5_m2_d16_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d16_ck_data,
-};
-
-static const char *usim_mux_fck_parents[] = {
- "sys_ck",
- "sys_d2_ck",
- "omap_96m_d2_fck",
- "omap_96m_d4_fck",
- "omap_96m_d8_fck",
- "omap_96m_d10_fck",
- "dpll5_m2_d4_ck",
- "dpll5_m2_d8_ck",
- "dpll5_m2_d16_ck",
- "dpll5_m2_d20_ck",
-};
-
-static struct ti_clk_mux usim_mux_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
- .reg = 0xc40,
- .module = TI_CLKM_CM,
- .parents = usim_mux_fck_parents,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk_composite usim_fck_data = {
- .mux = &usim_mux_fck_data,
- .gate = &usim_gate_fck_data,
-};
-
-static struct ti_clk usim_fck = {
- .name = "usim_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &usim_fck_data,
-};
-
-static int ssi_ssr_div_fck_3430es2_divs[] = {
- 0,
- 1,
- 2,
- 3,
- 4,
- 0,
- 6,
- 0,
- 8,
-};
-
-static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
- .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
- .parent = "corex2_fck",
- .bit_shift = 8,
- .dividers = ssi_ssr_div_fck_3430es2_divs,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite ssi_ssr_fck_3430e