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authorJernej Škrabec <jernej.skrabec@siol.net>2017-12-30 22:01:54 +0100
committerChen-Yu Tsai <wens@csie.org>2018-01-03 13:45:04 +0800
commit7dbc7f5f4904cfddc199af171ea095490a434f15 (patch)
tree0e8b3a79fe339717b8aea4ceae21e479576f7877 /drivers/clk
parentcf4881c1293516c1975606e8f2af7948789168b8 (diff)
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
TCON1 also has M divider, contrary to TCON0. And the mux is only 2 bits wide, instead of 3. Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> [wens@csie.org: Add description about mux width difference] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a83t.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 04a9c33f53f0..7d08015b980d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -504,8 +504,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const tcon1_parents[] = { "pll-video1" };
-static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,
- 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
+ 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);

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