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authorStephen Boyd <sboyd@codeaurora.org>2018-01-26 16:43:39 -0800
committerStephen Boyd <sboyd@codeaurora.org>2018-01-26 16:43:39 -0800
commitc43a52cfd27b20292d19d924eddfa5ff8dce87e5 (patch)
treed94ba5410091f6ad93c23cd98a6e1d5303710ec0 /drivers/clk
parent4d1d13a5ae8d468923106d5b05de407bc25cefa2 (diff)
parent6671507f0fbd582b4003f837ab791d03ade8e0f4 (diff)
parenta12aa8a68dfef5de181f2e555aa950a0ab05411f (diff)
parentbc27360b3c7aedfc385f7fc0527a42918bdeba51 (diff)
parentef0e5f382f50259f78089ccbb52e441e649d45aa (diff)
Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into clk-next
* clk-aspeed: clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs dt-bindings: clock: Add ASPEED constants * clk-lock-UP: clk: fix reentrancy of clk_enable() on UP systems * clk-mediatek: clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: mediatek: Fix all warnings for missing struct clk_onecell_data clk: mediatek: fixup test-building of MediaTek clock drivers clk: mediatek: group drivers under indpendent menu * clk-allwinner: clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU clk: sunxi-ng: add support for Allwinner H3 DE2 CCU dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL clk: sunxi-ng: Support fixed post-dividers on NM style clocks clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: Support fixed post-dividers on MP style clocks clk: sunxi: Use PTR_ERR_OR_ZERO()

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