path: root/drivers/fpga
diff options
authorJason Gunthorpe <jgunthorpe@obsidianresearch.com>2016-11-22 18:22:09 +0000
committerAlan Tull <atull@opensource.altera.com>2016-11-29 15:51:49 -0600
commit1d7f1589d341344c0c598b00de44891a7968c6a0 (patch)
treef1fd0d74131222096b584ebe16a11a9c0e476d34 /drivers/fpga
parent340c0c53ea3073107d5bb7a61f3158e50bf189e0 (diff)
fpga: Clarify how write_init works streaming modes
This interface was designed for streaming, but write_init's buf argument has an unclear purpose. Define it to be the first bytes of the bitstream. Each driver gets to set how many bytes (at most) it wants to see. Short bitstreams will be passed through as-is, while long ones will be truncated. The intent is to allow drivers to peek at the header before the transfer actually starts. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Alan Tull <atull@opensource.altera.com>
Diffstat (limited to 'drivers/fpga')
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index 79ce2eea44db..f0a69d3e60a5 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -53,10 +53,12 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
* Call the low level driver's write_init function. This will do the
* device-specific things to get the FPGA into the state where it is
- * ready to receive an FPGA image.
+ * ready to receive an FPGA image. The low level driver only gets to
+ * see the first initial_header_size bytes in the buffer.
- ret = mgr->mops->write_init(mgr, info, buf, count);
+ ret = mgr->mops->write_init(mgr, info, buf,
+ min(mgr->mops->initial_header_size, count));
if (ret) {
dev_err(dev, "Error preparing FPGA for writing\n");
diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
index ccd9fb23bd52..f8770af0f6b5 100644
--- a/drivers/fpga/socfpga-a10.c
+++ b/drivers/fpga/socfpga-a10.c
@@ -470,6 +470,7 @@ static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr)
static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = {
+ .initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4,
.state = socfpga_a10_fpga_state,
.write_init = socfpga_a10_fpga_write_init,
.write = socfpga_a10_fpga_write,

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