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authorAlex Deucher <alexander.deucher@amd.com>2013-01-03 19:54:34 -0500
committerAlex Deucher <alexander.deucher@amd.com>2013-01-03 19:54:34 -0500
commit4b681c2843cff55bac354abd1cad577d41e10807 (patch)
treec828b8cdf17a36a68b8d969005ccd2d8e00a063e /drivers/gpu
parent0a9069d34918659bc8a89e21e69e60b2b83291a3 (diff)
drm/radeon: fix typo in evergreen dma fence
SRBM write packet takes DW aligned registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f92f6bb18872..dcdff14dc13f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3231,7 +3231,7 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
/* flush HDP */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
- radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
+ radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
radeon_ring_write(ring, 1);
}

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