aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci
diff options
context:
space:
mode:
authorBjorn Helgaas <bhelgaas@google.com>2017-09-05 12:58:03 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-09-07 08:52:43 -0500
commit582ffae852400264b189da7dca9a5212dd3dab01 (patch)
tree3afb28f05a2e8e99e39bae7dc0d21a8d0ab87441 /drivers/pci
parentc7aca96aa48d59b08763452cf1881b7411876c59 (diff)
PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
Apparently the PCIe capability is at address 0x40 in config space of X-Gene v1 Root Ports. Add a definition of that and use the generic PCI_EXP_RTCTL offset into the capability. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pci-xgene.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index bd897479a215..af47ebd70e22 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -61,7 +61,7 @@
#define SZ_1T (SZ_1G*1024ULL)
#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
-#define ROOT_CAP_AND_CTRL 0x5C
+#define XGENE_V1_PCI_EXP_CAP 0x40
/* PCIe IP version */
#define XGENE_PCIE_IP_VER_UNKN 0
@@ -189,7 +189,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
* Avoid this by not claiming to support CRS.
*/
if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
- ((where & ~0x3) == ROOT_CAP_AND_CTRL))
+ ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
if (size <= 2)

Privacy Policy