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authorShaokun Zhang <zhangshaokun@hisilicon.com>2017-10-19 19:05:19 +0800
committerWill Deacon <will.deacon@arm.com>2017-10-19 17:06:35 +0100
commit2bab3cf9104c5ab80a1b9c706d81d997548401e4 (patch)
treea06bcc3b3f431ff9cbbfa016648c455c5bdac8c8 /drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
parent2940bc4333707a05e69b3ffd737bda0dc0c3004f (diff)
perf: hisi: Add support for HiSilicon SoC HHA PMU driver
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon SoC. This patch adds support for HHA PMU driver, Each HHA has own control, counter and interrupt registers and is an separate PMU. For each HHA PMU, it has 16-programable counters and each counter is free-running. Interrupt is supported to handle counter (48-bits) overflow. Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Anurup M <anurup.m@huawei.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c')
0 files changed, 0 insertions, 0 deletions

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