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authorRafał Miłecki <zajec5@gmail.com>2015-04-05 18:39:27 +0200
committerKalle Valo <kvalo@codeaurora.org>2015-04-07 20:18:10 +0300
commitf56d9e23b78e311fbd992a1bd80b8bf2adaee29b (patch)
tree25a92db4ae796d33dcaeecc92284b87bb4dda6e8 /drivers/ssb
parent61b559dea40ec1712be4a0ea712a2922a8f38588 (diff)
ssb: add delay after PCI reset to fix SoC reboots
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/ssb')
-rw-r--r--drivers/ssb/driver_pcicore.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
index d75b72ba2672..15a7ee3859dd 100644
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
+ /*
+ * Accessing PCI config without a proper delay after devices reset (not
+ * GPIO reset) was causing reboots on WRT300N v1.0.
+ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
+ * completely. Flushing all writes was also tested but with no luck.
+ */
+ if (pc->dev->bus->chip_id == 0x4704)
+ usleep_range(1000, 2000);
+
/* Enable PCI bridge BAR0 prefetch and burst */
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);

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