path: root/include/drm/drm_dp_helper.h
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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-18 15:32:40 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-22 22:34:46 +0200
commit1a644cd47ca0c40a9210db170bd0630031c3a60b (patch)
tree03144ce14e66c9b155369b5af92227ac8080e5f1 /include/drm/drm_dp_helper.h
parent0f037bdee1a12947a0c55b21a05f57793332bc07 (diff)
drm: extract dp link train delay functions from radeon
This requires a few changes since that dpcd value is above the range currently cached by radeon. I've check the dp specs, and above 0xf there's a big gap and nothing that looks like we should cache it while a given device is plugged in. It's also the same value that i915.ko uses. Hence extend the various dpcd arrays in the radeon driver, use proper symbolic constants where applicable (one place overallocated the dpcd array to 25 bytes). Then also drop the rd_interval cache - radeon_dp_link_train_init re-reads the dpcd block, so the values we'll consume in train_cr and train_ce will always be fresh. To avoid needless diff-churn, #define the old size of dpcd as the new one and keep it around. v2: Alex Deucher noticed one place where I've forgotten to replace 8 with DP_RECEIVER_CAP_SIZE. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm/drm_dp_helper.h')
1 files changed, 5 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 57e6dbd0580c..60bd8d3ae6eb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -25,6 +25,7 @@
#include <linux/types.h>
#include <linux/i2c.h>
+#include <linux/delay.h>
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
@@ -333,4 +334,8 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
+void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
#endif /* _DRM_DP_HELPER_H_ */

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