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authorPadmavathi Venna <padma.v@samsung.com>2013-06-18 00:02:17 +0900
committerKukjin Kim <kgene.kim@samsung.com>2013-06-19 03:28:41 +0900
commit1241ef94ccc3aeaeecf73b2889efd9bcd6ffa4f7 (patch)
tree14bc5b64d02738fd95bc2d626f9374b72cf090a6 /include/dt-bindings/clk
parent3799279f70f1aa4fc452f1af59031122c93522aa (diff)
clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'include/dt-bindings/clk')
-rw-r--r--include/dt-bindings/clk/exynos-audss-clk.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
new file mode 100644
index 000000000000..8279f427c60f
--- /dev/null
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS 0
+#define EXYNOS_MOUT_I2S 1
+#define EXYNOS_DOUT_SRP 2
+#define EXYNOS_DOUT_AUD_BUS 3
+#define EXYNOS_DOUT_I2S 4
+#define EXYNOS_SRP_CLK 5
+#define EXYNOS_I2S_BUS 6
+#define EXYNOS_SCLK_I2S 7
+#define EXYNOS_PCM_BUS 8
+#define EXYNOS_SCLK_PCM 9
+
+#define EXYNOS_AUDSS_MAX_CLKS 10
+
+#endif

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