path: root/include/dt-bindings/clock/imx6sx-clock.h
diff options
authorShengjiu Wang <shengjiu.wang@freescale.com>2015-10-10 18:15:06 +0800
committerShawn Guo <shawnguo@kernel.org>2015-10-12 21:55:59 +0800
commit84a87250ee4e4f7cf5865be9757e2ea758e5cae3 (patch)
treea161d5d1d3fe98a43045857e906cc45ab2257666 /include/dt-bindings/clock/imx6sx-clock.h
parentab4c6a240731f701806154fe3e0cfb8a3abec369 (diff)
clk: imx6: Add SPDIF_GCLK clock in clock tree
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock/imx6sx-clock.h')
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 995709119ec5..36f0324902a5 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -274,6 +274,7 @@
#define IMX6SX_PLL5_BYPASS 261
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
-#define IMX6SX_CLK_CLK_END 264
+#define IMX6SX_CLK_SPDIF_GCLK 264
+#define IMX6SX_CLK_CLK_END 265

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