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authorStephen Boyd <sboyd@codeaurora.org>2014-07-10 09:18:29 +0100
committerStephen Boyd <sboyd@codeaurora.org>2014-07-11 13:21:22 -0700
commit5f775498bdc44f294c37eaa7a205335e3b6667df (patch)
treec6f015755676ae4d12731a587aef7b654dbcec0f /include/dt-bindings/reset
parent7f9b72ae972fd6395debeb2f859b7cadf2c2466e (diff)
clk: qcom: Fully support apq8064 global clock control
Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings/reset')
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8960.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index 07edd0e65eed..47c8686955da 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -114,5 +114,21 @@
#define SFAB_SMPSS_S_RESET 97
#define PRNG_RESET 98
#define RIVA_RESET 99
+#define USB_HS3_RESET 100
+#define USB_HS4_RESET 101
+#define CE3_RESET 102
+#define PCIE_EXT_PCI_RESET 103
+#define PCIE_PHY_RESET 104
+#define PCIE_PCI_RESET 105
+#define PCIE_POR_RESET 106
+#define PCIE_HCLK_RESET 107
+#define PCIE_ACLK_RESET 108
+#define CE3_H_RESET 109
+#define SFAB_CE3_M_RESET 110
+#define SFAB_CE3_S_RESET 111
+#define SATA_RESET 112
+#define CE3_SLEEP_RESET 113
+#define GSS_SLP_RESET 114
+#define GSS_RESET 115
#endif

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