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authorThierry Reding <treding@nvidia.com>2015-08-06 14:20:31 +0200
committerThierry Reding <treding@nvidia.com>2015-08-13 17:05:28 +0200
commit11cec15bf3fb498206ef63b1fa26c27689e02d0e (patch)
tree330bd3eff26a1915e86b5e896cdee4db2c909896 /include/soc
parent4080e99b8341f81c4ed1e17d8ef44d171c473a1b (diff)
iommu/tegra-smmu: Parameterize number of TLB lines
The number of TLB lines was increased from 16 on Tegra30 to 32 on Tegra114 and later. Parameterize the value so that the initial default can be set accordingly. On Tegra30, initializing the value to 32 would effectively disable the TLB and hence cause massive latencies for memory accesses translated through the SMMU. This is especially noticeable for isochronuous clients such as display, whose FIFOs would continuously underrun. Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support") Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/tegra/mc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index d6c3190ec852..8cb3a7ecd6f8 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -61,6 +61,7 @@ struct tegra_smmu_soc {
bool supports_round_robin_arbitration;
bool supports_request_limit;
+ unsigned int num_tlb_lines;
unsigned int num_asids;
};

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