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authorMikko Perttunen <mperttunen@nvidia.com>2015-03-12 15:47:55 +0100
committerThierry Reding <treding@nvidia.com>2015-05-04 14:21:21 +0200
commit6ea2609ab386f6bfeebc39e1418b7497a9deb55c (patch)
treedbb31e0eb394cfa6079e1bfbadf571b5dc772f12 /include/soc
parent405990c7e834913554482538321f16f457dda50e (diff)
soc/tegra: fuse: Add RAM code reader helper
Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/tegra/fuse.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index b5f7b5f8d008..b019e3465f11 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -56,6 +56,7 @@ struct tegra_sku_info {
};
u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
u32 tegra_read_chipid(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);

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