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authorDave Airlie <airlied@redhat.com>2017-10-12 10:20:03 +1000
committerDave Airlie <airlied@redhat.com>2017-10-12 10:20:03 +1000
commitc5c7bc71a0e6bc382744497e45c6c70503f9d7e6 (patch)
tree35a00018aa6165ce0c17e2e2d4aa398ffea119bc /include/uapi/drm
parent418da17214aca5ef5f0b6f7588905ee7df92f98f (diff)
parente18063e88bd579c479a2b45820be6c4625f841c3 (diff)
Merge tag 'drm-intel-next-2017-09-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
2nd batch of v4.15 features: - lib/scatterlist updates, use for userptr allocations (Tvrtko) - Fixed point wrapper cleanup (Mahesh) - Gen9+ transition watermarks, watermark optimization and fixes (Mahesh) - Display IPC (Isochronous Priority Control) support (Mahesh) - GEM workaround fixes (Oscar) - GVT: PCI config sanitize series (Changbin) - GVT: Workload submission error handling series (Fred) - PSR fixes and refactoring (Rodrigo) - HWSP based optimizations (Chris) - Private PAT management (Zhi) - IRQ handling fixes and refactoring (Ville) - Module parameter refactoring and variable name clash fix (Michal) - Execlist refactoring, incomplete request unwinding on reset (Chris) - GuC scheduling improvements (Michal) - OA updates (Lionel) - Coffeelake out of alpha support (Rodrigo) - seqno fixes (Chris) - Execlist refactoring (Mika) - DP and DP MST cleanups (Dhinakaran) - Cannonlake slice/sublice config (Ben) - Numerous fixes all around (Everyone) * tag 'drm-intel-next-2017-09-29' of git://anongit.freedesktop.org/drm/drm-intel: (168 commits) drm/i915: Update DRIVER_DATE to 20170929 drm/i915: Use memset64() to prefill the GTT page drm/i915: Also discard second CRC on gen8+ platforms. drm/i915/psr: Set frames before SU entry for psr2 drm/dp: Add defines for latency in sink drm/i915: Allow optimized platform checks drm/i915: Avoid using dev_priv->info.gen directly. i915: Use %pS printk format for direct addresses drm/i915/execlists: Notify context-out for lost requests drm/i915/cnl: Add support slice/subslice/eu configs drm/i915: Compact device info access by a small re-ordering drm/i915: Add IS_PLATFORM macro drm/i915/selftests: Try to recover from a wedged GPU during reset tests drm/i915/huc: Reorganize HuC authentication drm/i915: Fix default values of some modparams drm/i915: Extend I915_PARAMS_FOR_EACH with default member value drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible drm/i915: Enable scanline read based on frame timestamps drm/i915/execlists: Microoptimise execlists_cancel_port_request() drm/i915: Don't rmw PIPESTAT enable bits ...
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/i915_drm.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d8d10d932759..fe25a01c81f2 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1308,14 +1308,16 @@ struct drm_i915_reg_read {
* be specified
*/
__u64 offset;
+#define I915_REG_READ_8B_WA BIT(0)
+
__u64 val; /* Return value */
};
/* Known registers:
*
* Render engine timestamp - 0x2358 + 64bit - gen7+
* - Note this register returns an invalid value if using the default
- * single instruction 8byte read, in order to workaround that use
- * offset (0x2538 | 1) instead.
+ * single instruction 8byte read, in order to workaround that pass
+ * flag I915_REG_READ_8B_WA in offset field.
*
*/
@@ -1509,6 +1511,11 @@ struct drm_i915_perf_oa_config {
__u32 n_boolean_regs;
__u32 n_flex_regs;
+ /*
+ * These fields are pointers to tuples of u32 values (register
+ * address, value). For example the expected length of the buffer
+ * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+ */
__u64 mux_regs_ptr;
__u64 boolean_regs_ptr;
__u64 flex_regs_ptr;

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