aboutsummaryrefslogtreecommitdiffstats
path: root/include/video
diff options
context:
space:
mode:
authorKrzysztof Kozlowski <k.kozlowski@samsung.com>2015-04-07 22:28:50 +0900
committerInki Dae <inki.dae@samsung.com>2015-04-13 11:39:42 +0900
commit1c363c7cccf64128087002b0779986ad16aff6dc (patch)
tree1f1188f0361bf0acde927ae5c4e0cb3843169f19 /include/video
parentd1222842c1c7c2760ebd412238d9bb6234e6742c (diff)
drm/exynos: Enable DP clock to fix display on Exynos5250 and other
After adding display power domain for Exynos5250 in commit 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the display on Chromebook Snow and others stopped working after boot. The reason for this suggested Andrzej Hajda: the DP clock was disabled. This clock is required by Display Port and is enabled by bootloader. However when FIMD driver probing was deferred, the display power domain was turned off. This effectively reset the value of DP clock enable register. When exynos-dp is later probed, the clock is not enabled and display is not properly configured: exynos-dp 145b0000.dp-controller: Timeout of video streamclk ok exynos-dp 145b0000.dp-controller: unable to config video Fixes: 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reported-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'include/video')
-rw-r--r--include/video/samsung_fimd.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index 513242827b07..0530e5a4c6b1 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -441,6 +441,12 @@
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
+/* Display port clock control */
+#define DP_MIE_CLKCON 0x27c
+#define DP_MIE_CLK_DISABLE 0x0
+#define DP_MIE_CLK_DP_ENABLE 0x2
+#define DP_MIE_CLK_MIE_ENABLE 0x3
+
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4

Privacy Policy