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authorLinus Torvalds <torvalds@linux-foundation.org>2017-02-20 17:26:11 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2017-02-20 17:26:11 -0800
commit85adbcd54f0982040c8cc7a086f01554b8f64427 (patch)
treeb5210dcee692b928bd133541dba31f487e246ac8 /include
parentf790bd9c8e826434ab6c326b225276ed0f73affe (diff)
parent57f22cd29cf1b4ff2aea8505eae2d3ed71ca5de4 (diff)
Merge tag 'spi-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "This release is mainly a collection of driver specific updates, including a few nice cleanups to make drivers use more core features. - automatically use the parent device to allocate DMA buffers if there wasn't an explicitly configured device. - fixes for leaks on allocation. - a small piece of the start of SPI slave support, a feature that's been on the cards for over a decade!" * tag 'spi-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (55 commits) spi: spi-ti-qspi: Fix error handling spi: spi-ti-qspi: Fix error handling spi: lantiq-ssc: activate under COMPILE_TEST spi: armada-3700: Remove spi_master_put in a3700_spi_remove() spi: ti-qspi: revise ti_qspi_probe() failure flow spi: spi-ep93xx: simplify GPIO chip selects spi: rspi: Replaces "n" by "len" in qspi_transfer_*() spi: rspi: Fixes bogus received byte in qspi_transfer_in() spi: bcm-qspi: Remove unnecessary platform_set_drvdata() spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance spi: lantiq-ssc: add support for Lantiq SSC SPI controller spi: s3c64xx: fix inconsistency between binding and driver spi: armada-3700: Remove .owner field for driver spi: bcm-qspi: Added mspi read fallback in bcm_qspi_flash_read() spi: fix device-node leaks spi: mediatek: Only do dma for 4-byte aligned buffers spi: When no dma_chan map buffers with spi_master's parent spi: pca2xx-pci: Allow MSI spi: pxa2xx: Prepare for edge-triggered interrupts spi: pxa2xx: Add support for Intel Gemini Lake ...
Diffstat (limited to 'include')
-rw-r--r--include/linux/platform_data/spi-ep93xx.h17
-rw-r--r--include/linux/pxa2xx_ssp.h14
2 files changed, 10 insertions, 21 deletions
diff --git a/include/linux/platform_data/spi-ep93xx.h b/include/linux/platform_data/spi-ep93xx.h
index 9bb63ac13f04..171a271c2cbd 100644
--- a/include/linux/platform_data/spi-ep93xx.h
+++ b/include/linux/platform_data/spi-ep93xx.h
@@ -5,25 +5,14 @@ struct spi_device;
/**
* struct ep93xx_spi_info - EP93xx specific SPI descriptor
- * @num_chipselect: number of chip selects on this board, must be
- * at least one
+ * @chipselect: array of gpio numbers to use as chip selects
+ * @num_chipselect: ARRAY_SIZE(chipselect)
* @use_dma: use DMA for the transfers
*/
struct ep93xx_spi_info {
+ int *chipselect;
int num_chipselect;
bool use_dma;
};
-/**
- * struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device
- * @setup: setup the chip select mechanism
- * @cleanup: cleanup the chip select mechanism
- * @cs_control: control the device chip select
- */
-struct ep93xx_spi_chip_ops {
- int (*setup)(struct spi_device *spi);
- void (*cleanup)(struct spi_device *spi);
- void (*cs_control)(struct spi_device *spi, int value);
-};
-
#endif /* __ASM_MACH_EP93XX_SPI_H */
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 2d6f0c39ed68..a0522328d7aa 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -90,9 +90,9 @@
#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
-#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
-#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
#define RX_THRESH_CE4100_DFLT 2
#define TX_THRESH_CE4100_DFLT 2
@@ -106,9 +106,9 @@
#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
/* QUARK_X1000 SSCR0 bit definition */
-#define QUARK_X1000_SSCR0_DSS (0x1F) /* Data Size Select (mask) */
-#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
-#define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */
+#define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */
+#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
+#define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */
#define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */
#define RX_THRESH_QUARK_X1000_DFLT 1
@@ -121,8 +121,8 @@
#define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
#define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */
#define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
-#define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */
-#define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */
+#define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */
+#define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */
/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */

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