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-rw-r--r--include/soc/at91/at91rm9200_sdramc.h63
-rw-r--r--include/soc/imx/revision.h37
-rw-r--r--include/soc/imx/timer.h26
-rw-r--r--include/soc/tegra/emc.h19
-rw-r--r--include/soc/tegra/fuse.h1
-rw-r--r--include/soc/tegra/mc.h20
-rw-r--r--include/soc/tegra/pmc.h2
7 files changed, 102 insertions, 66 deletions
diff --git a/include/soc/at91/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f458f1b..000000000000
--- a/include/soc/at91/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (SDRAMC only) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_SDRAMC_H
-#define AT91RM9200_SDRAMC_H
-
-/* SDRAM Controller registers */
-#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
-#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
-#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
-#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
-#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
-#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
-#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
-#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
-#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
-
-#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
-#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
-
-#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
-#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
-#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
-#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
-#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
-#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
-#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
-#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
-#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
-#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
-#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
-#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
-#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
-#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
-#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
-#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
-#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
-
-#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
-#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
-#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
-#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
-#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
-#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
-
-#endif
diff --git a/include/soc/imx/revision.h b/include/soc/imx/revision.h
new file mode 100644
index 000000000000..9ea346924c35
--- /dev/null
+++ b/include/soc/imx/revision.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2015 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_IMX_REVISION_H__
+#define __SOC_IMX_REVISION_H__
+
+#define IMX_CHIP_REVISION_1_0 0x10
+#define IMX_CHIP_REVISION_1_1 0x11
+#define IMX_CHIP_REVISION_1_2 0x12
+#define IMX_CHIP_REVISION_1_3 0x13
+#define IMX_CHIP_REVISION_1_4 0x14
+#define IMX_CHIP_REVISION_1_5 0x15
+#define IMX_CHIP_REVISION_2_0 0x20
+#define IMX_CHIP_REVISION_2_1 0x21
+#define IMX_CHIP_REVISION_2_2 0x22
+#define IMX_CHIP_REVISION_2_3 0x23
+#define IMX_CHIP_REVISION_3_0 0x30
+#define IMX_CHIP_REVISION_3_1 0x31
+#define IMX_CHIP_REVISION_3_2 0x32
+#define IMX_CHIP_REVISION_3_3 0x33
+#define IMX_CHIP_REVISION_UNKNOWN 0xff
+
+int mx27_revision(void);
+int mx31_revision(void);
+int mx35_revision(void);
+int mx51_revision(void);
+int mx53_revision(void);
+
+unsigned int imx_get_soc_revision(void);
+void imx_print_silicon_rev(const char *cpu, int srev);
+
+#endif /* __SOC_IMX_REVISION_H__ */
diff --git a/include/soc/imx/timer.h b/include/soc/imx/timer.h
new file mode 100644
index 000000000000..bbbafd65f464
--- /dev/null
+++ b/include/soc/imx/timer.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2015 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_IMX_TIMER_H__
+#define __SOC_IMX_TIMER_H__
+
+enum imx_gpt_type {
+ GPT_TYPE_IMX1, /* i.MX1 */
+ GPT_TYPE_IMX21, /* i.MX21/27 */
+ GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */
+ GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */
+};
+
+/*
+ * This is a stop-gap solution for clock drivers like imx1/imx21 which call
+ * mxc_timer_init() to initialize timer for non-DT boot. It can be removed
+ * when these legacy non-DT support is converted or dropped.
+ */
+void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type);
+
+#endif /* __SOC_IMX_TIMER_H__ */
diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h
new file mode 100644
index 000000000000..f6db33b579ec
--- /dev/null
+++ b/include/soc/tegra/emc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_EMC_H__
+#define __SOC_TEGRA_EMC_H__
+
+struct tegra_emc;
+
+int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
+ unsigned long rate);
+void tegra_emc_complete_timing_change(struct tegra_emc *emc,
+ unsigned long rate);
+
+#endif /* __SOC_TEGRA_EMC_H__ */
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index b5f7b5f8d008..b019e3465f11 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -56,6 +56,7 @@ struct tegra_sku_info {
};
u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
u32 tegra_read_chipid(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 63deb8d9f82a..1ab2813273cd 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -20,6 +20,12 @@ struct tegra_smmu_enable {
unsigned int bit;
};
+struct tegra_mc_timing {
+ unsigned long rate;
+
+ u32 *emem_data;
+};
+
/* latency allowance */
struct tegra_mc_la {
unsigned int reg;
@@ -40,6 +46,7 @@ struct tegra_mc_client {
};
struct tegra_smmu_swgroup {
+ const char *name;
unsigned int swgroup;
unsigned int reg;
};
@@ -71,6 +78,7 @@ struct tegra_smmu;
struct tegra_smmu *tegra_smmu_probe(struct device *dev,
const struct tegra_smmu_soc *soc,
struct tegra_mc *mc);
+void tegra_smmu_remove(struct tegra_smmu *smmu);
#else
static inline struct tegra_smmu *
tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
@@ -78,13 +86,17 @@ tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
{
return NULL;
}
+
+static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
+{
+}
#endif
struct tegra_mc_soc {
const struct tegra_mc_client *clients;
unsigned int num_clients;
- const unsigned int *emem_regs;
+ const unsigned long *emem_regs;
unsigned int num_emem_regs;
unsigned int num_address_bits;
@@ -102,6 +114,12 @@ struct tegra_mc {
const struct tegra_mc_soc *soc;
unsigned long tick;
+
+ struct tegra_mc_timing *timings;
+ unsigned int num_timings;
};
+void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
+unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
+
#endif /* __SOC_TEGRA_MC_H__ */
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index 65a93273e72f..f5c0de43a5fa 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -26,8 +26,6 @@
struct clk;
struct reset_control;
-void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
-
#ifdef CONFIG_PM_SLEEP
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);

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