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2018-01-07riscv: rename SR_* constants to match the specChristoph Hellwig6-17/+17
2018-01-07riscv: remove CONFIG_MMU ifdefsChristoph Hellwig4-24/+0
2018-01-07RISC-V: Make __NR_riscv_flush_icache visible to userspacePalmer Dabbelt5-30/+27
2018-01-07RISC-V: Add a basic defconfigKarsten Merker1-0/+75
2017-12-11RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt1-11/+0
2017-12-11RISC-V: Resurrect smp_mb__after_spinlock()Palmer Dabbelt1-0/+19
2017-12-11RISC-V: Logical vs Bitwise typoDan Carpenter1-1/+1
2017-12-05bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program typeHendrik Brueckner1-0/+1
2017-12-01RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt12-21/+39
2017-12-01RISC-V: __io_writes should respect the length argumentPalmer Dabbelt1-1/+1
2017-12-01RISC-V: User-Visible ChangesPalmer Dabbelt19-34/+392
2017-12-01RISC-V: __io_writes should respect the length argumentPalmer Dabbelt1-1/+1
2017-11-30RISC-V: Clean up an unused includePalmer Dabbelt1-1/+0
2017-11-30RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman8-0/+105
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman8-30/+174
2017-11-30RISC-V: Add missing includeOlof Johansson1-0/+1
2017-11-30RISC-V: Use define for get_cycles like other architecturesOlof Johansson1-1/+2
2017-11-30RISC-V: Provide stub of setup_profiling_timer()Olof Johansson1-0/+7
2017-11-30RISC-V: Export some expected symbols for modulesOlof Johansson3-0/+6
2017-11-30RISC-V: move empty_zero_page definition to C and export itOlof Johansson2-3/+3
2017-11-30RISC-V: io.h: type fixes for warningsOlof Johansson2-8/+10
2017-11-30RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macrosOlof Johansson2-9/+9
2017-11-30RISC-V: use generic serial.hOlof Johansson1-0/+1
2017-11-28RISC-V: remove spin_unlock_wait()Palmer Dabbelt1-9/+0
2017-11-28RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt1-1/+4
2017-11-28RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt1-1/+1
2017-11-28RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt1-1/+1
2017-11-28RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt1-8/+0
2017-11-28RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt1-15/+0
2017-11-28RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt1-2/+7
2017-11-28RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt1-47/+47
2017-11-27RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman6-1/+113
2017-11-27RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt1-2/+0
2017-11-15Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds102-0/+9776
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt9-0/+579
2017-09-26RISC-V: User-facing APIPalmer Dabbelt27-0/+1687
2017-09-26RISC-V: Paging and MMUPalmer Dabbelt8-0/+1192
2017-09-26RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt9-0/+566
2017-09-26RISC-V: Task implementationPalmer Dabbelt9-0/+1243
2017-09-26RISC-V: ELF and module implementationPalmer Dabbelt4-0/+187
2017-09-26RISC-V: Generic library routines and assemblyPalmer Dabbelt11-0/+1389
2017-09-26RISC-V: Atomic and Locking CodePalmer Dabbelt10-0/+1423
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt15-0/+1524

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