path: root/drivers/clk/bcm/clk-iproc.h
AgeCommit message (Collapse)AuthorFilesLines
2017-12-28clk: iproc: Allow iproc pll to runtime calculate vco parametersLori Hikichi1-0/+5
Add the ability for the iproc pll to calculate the pll parameters at runtime instead of only using predefined tables. This ability allows the clock users to select from the full range of vco frequencies. The old method of table based programming is retained so that existing users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM will need to be set to enable the new runtime calculation method. Currently, this is only being enabled for the audio pll. This feature also revealed a problem with the driver using the round_rate api. The round_rate api does not allow for frequencies larger than 2^31 to be returned. Those large frequencies are interpreted as an error code. Therefore, we are moving to the determine_rate api which solves this problem. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: iproc: Remove __init from headerRay Jui1-11/+11
Remove __init macro from all function prototypes in clk-iproc.h Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: iproc: Add support for Cygnus audio clocksSimran Rai1-0/+21
This patch adds support for Broadcom Cygnus audio PLL and leaf clocks Signed-off-by: Simran Rai <ssimran@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Separate status and control variablesJon Mason1-0/+6
Some PLLs have separate registers for Status and Control. The means the pll_base needs to be split into 2 new variables, so that those PLLs can specify device tree registers for those independently. Also, add a new driver flag to identify this presence of the split, and let the driver know that additional registers need to be used. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Split off dig_filterJon Mason1-1/+9
The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Add PWRCTRL supportJon Mason1-0/+6
Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN. Signed-off-by: Jon Mason <jonmason@broadcom.com> [sboyd@codeaurora.org: Remove useless parentheses] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-18clk: iproc: add initial common clock supportRay Jui1-0/+178
This adds basic and generic support for various iProc PLLs and clocks including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks. SoCs under the iProc architecture can define their specific register offsets and clock parameters for their PLL and clock controllers. These parameters can be passed as arugments into the generic iProc PLL and clock setup functions Derived from code originally provided by Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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