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path: root/drivers/clk/clk-aspeed.c
AgeCommit message (Expand)AuthorFilesLines
2018-01-26clk: aspeed: Handle inverse polarity of USB port 1 clock gateBenjamin Herrenschmidt1-3/+12
2018-01-26clk: aspeed: Fix return value check in aspeed_cc_init()Wei Yongjun1-1/+1
2018-01-26clk: aspeed: Add reset controllerJoel Stanley1-1/+81
2018-01-26clk: aspeed: Register gated clocksJoel Stanley1-0/+130
2018-01-26clk: aspeed: Add platform driver and register PLLsJoel Stanley1-0/+130
2018-01-26clk: aspeed: Register core clocksJoel Stanley1-0/+177
2018-01-26clk: Add clock driver for ASPEED BMC SoCsJoel Stanley1-0/+141

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