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AgeCommit message (Expand)AuthorFilesLines
2017-12-26clk: use atomic runtime pm api in clk_core_is_enabledDong Aisheng1-1/+2
2017-12-26clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang1-0/+1
2017-12-23clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2017-12-21clk: si5351: Do not enable parent clocks on probeSergej Sawazki1-26/+9
2017-12-21clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki1-1/+1
2017-12-21clk: si5351: Apply PLL soft reset before enabling the outputsSergej Sawazki1-0/+29
2017-12-21clk: si5351: Add DT property to enable PLL resetSergej Sawazki1-0/+3
2017-12-21clk: si5351: implement remove handlerAlexey Khoroshilov1-0/+13
2017-12-21clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen1-3/+7
2017-12-21clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen1-5/+24
2017-12-21clk: Don't touch hardware when reparenting during registrationStephen Boyd1-2/+5
2017-12-21clk: mediatek: fixup test-building of MediaTek clock driversSean Wang1-1/+1
2017-12-21clk: mediatek: group drivers under indpendent menuSean Wang1-46/+50
2017-12-21clk: at91: pmc: Support backup for programmable clocksRomain Izard3-0/+39
2017-12-21clk: at91: pmc: Save SCSR during suspendRomain Izard1-2/+2
2017-12-21clk: at91: pmc: Wait for clocks when resumingRomain Izard1-8/+16
2017-12-21clk: qcom: ipq8074: add misc resets for PCIE and NSSAbhishek Sahu1-0/+42
2017-12-21clk: qcom: ipq8074: add GP and Crypto clocksAbhishek Sahu1-0/+199
2017-12-21clk: qcom: ipq8074: add NSS ethernet port clocksAbhishek Sahu1-0/+1288
2017-12-21clk: qcom: ipq8074: add NSS clocksAbhishek Sahu1-0/+1034
2017-12-21clk: qcom: ipq8074: add PCIE, USB and SDCC clocksAbhishek Sahu1-0/+994
2017-12-21clk: qcom: ipq8074: add remaining PLL’sAbhishek Sahu1-1/+191
2017-12-21clk: qcom: ipq8074: fix missing GPLL0 divider widthAbhishek Sahu1-0/+1
2017-12-21clk: qcom: add parent map for regmap muxAbhishek Sahu4-11/+18
2017-12-21clk: qcom: add read-only divider operationsAbhishek Sahu2-0/+30
2017-12-21clk: imx51: uart4, uart5 gates only exist on imx50, imx53Philipp Zabel1-4/+8
2017-12-21clk: qoriq: add more divider clocks supportYuantian Tang1-1/+8
2017-12-21clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocksGregory CLEMENT1-4/+217
2017-12-21clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFSGregory CLEMENT1-9/+73
2017-12-21clk: mvebu: armada-37xx-periph: cosmetic changesGregory CLEMENT1-8/+9
2017-12-21clk: sprd: add clocks support for SC9860Chunyan Zhang3-0/+1987
2017-12-21clk: sprd: add adjustable pll supportChunyan Zhang3-0/+375
2017-12-21clk: sprd: add composite clock supportChunyan Zhang3-0/+112
2017-12-21clk: sprd: add divider clock supportChunyan Zhang3-0/+166
2017-12-21clk: sprd: add mux clock supportChunyan Zhang3-0/+151
2017-12-21clk: sprd: add gate clock supportChunyan Zhang3-0/+171
2017-12-21clk: sprd: Add common infrastructureChunyan Zhang6-0/+143
2017-12-21clk: move clock common macros out from vendor directoriesChunyan Zhang2-47/+0
2017-12-19clk: fix set_rate_range when current rate is out of rangeJerome Brunet1-4/+33
2017-12-19clk: add clk_rate_exclusive apiJerome Brunet1-0/+172
2017-12-19clk: cosmetic changes to clk_summary debugfs entryJerome Brunet1-3/+4
2017-12-19clk: add clock protection mechanism to clk coreJerome Brunet1-7/+112
2017-12-19clk: use round rate to bail out early in set_rateJerome Brunet1-2/+23
2017-12-19clk: rework calls to round and determine rate callbacksJerome Brunet1-30/+52
2017-12-19clk: add clk_core_set_phase_nolock functionJerome Brunet1-12/+21
2017-12-19clk: take the prepare lock out of clk_core_set_parentJerome Brunet1-20/+20
2017-12-19clk: fix incorrect usage of ENOSYSJerome Brunet1-1/+1
2017-12-19clk: sunxi: sun9i-mmc: Implement reset callback for reset controlsChen-Yu Tsai1-0/+12
2017-12-19clk: check ops pointer on clock registerJerome Brunet1-0/+7
2017-12-14clk: ti: Drop legacy clk-3xxx-legacy codeTony Lindgren8-5078/+0

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