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2018-01-26Merge remote-tracking branch 'spi/topic/xilinx' into spi-nextMark Brown1-0/+1
2018-01-26Merge remote-tracking branches 'spi/topic/pxa2xx', 'spi/topic/s3c64xx', ↵Mark Brown5-41/+103
'spi/topic/sh-msiof', 'spi/topic/sirf' and 'spi/topic/sun6i' into spi-next
2018-01-26Merge remote-tracking branches 'spi/topic/fsl-dspi', 'spi/topic/imx', ↵Mark Brown5-14/+32
'spi/topic/jcore', 'spi/topic/meson' and 'spi/topic/orion' into spi-next
2018-01-26Merge remote-tracking branches 'spi/topic/a3700', 'spi/topic/atmel', ↵Mark Brown5-67/+188
'spi/topic/bcm53xx', 'spi/topic/davinci' and 'spi/topic/dw' into spi-next
2018-01-26Merge remote-tracking branches 'spi/fix/imx' and 'spi/fix/sh-msiof' into ↵Mark Brown2-3/+24
spi-linus
2018-01-26spi: dw: Remove unused members from struct chip_dataJarkko Nikula1-2/+0
Local struct chip_data has two members that are not used: - cs. Looks like was never used - enable_dma. Became unused by the commit f89a6d8f43eb ("spi: dw-mid: move to use core SPI DMA mappings"). Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-26spi: orion: Fix a resource leak if the optional "axi" clk is deferredChristophe Jaillet1-5/+8
If the optional "axi" clk is deferred, we still need to undo some initialisation. Especially 'master' must be released. It will be reallocated the next time 'orion_spi_probe()' is called. Add a new label to clean what needs to be cleaned and rename another label to improve the names used. Fixes: 92ae112e477a ("spi: orion: Fix clock resource by adding an optional bus clock") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-24spi: a3700: Remove endianness swapping for full-duplex transfersMaxime Chevallier1-7/+6
Fixes the following sparse warnings : line 767: warning: incorrect type in assignment (different base types) line 767: expected unsigned int [unsigned] [assigned] [usertype] val_out line 767: got restricted __le32 [usertype] <noident> line 776: warning: cast to restricted __le32 This takes advantage of readl/writel to do the endianness reordering, and removes an extra variable in the function. Fixes: f68a7dcb91b7 ("spi: a3700: Add full-duplex support") Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-24spi: a3700: Remove endianness swapping functions when accessing FIFOsMaxime Chevallier1-3/+2
Fixes the following sparse warnings : line 504: warning: incorrect type in assignment (different base types) line 504: expected unsigned int [unsigned] [usertype] val line 504: got restricted __le32 [usertype] <noident> line 527: warning: cast to restricted __le32 This is solved by removing endian-converson functions, since the converted values are going through readl/writel anyway, which take care of the conversion. Fixes: 6fd6fd68c9e2 ("spi: armada-3700: Fix padding when sending not 4-byte aligned data") Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-18spi: a3700: Add full-duplex supportMaxime Chevallier1-12/+73
The armada 3700 SPI controller has support for full-duplex transfers, but it can only be done without using the hardware FIFOs. A full duplex transfer is done by shifting 4 bytes at a time, or even one byte at a time for transfers less than 4 bytes long. While this method is perfectly suitable for small transfers, it is still slower than using the FIFOs. This commit implement full-duplex support, making sure that half-duplex transfers are still done using the FIFOs with the existing method. Some setup functions were moved around to make sure the controller is properly configured before beginning each transfer. This was tested on EspressoBin with a logical analyser, and a simple setup where MISO is connected on MOSI. Transfers were made from userspace using spidev and spi-pipe from the spi-tools project Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-18spi: a3700: Allow to enable or disable FIFO modeMaxime Chevallier1-3/+6
The armada 3700 SPI controller allows to make transfers without using the 32 bytes RFIFO and WFIFO. This commit enable switching between FIFO and non-FIFO mode, which is necessary to implement full-duplex transfers. Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-18spi: a3700: Set frequency limits at startupMaxime Chevallier1-0/+7
Armada 3700 SPI controller has an internal clock divider which can divide the parent clock frequency by up to 30. This patch sets the limits in the spi_controller fields so that we can detect when a non-supported frequency is requested by a device for a transfer. Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-18spi: a3700: Clear DATA_OUT when performing a readMaxime Chevallier1-0/+5
When performing a read using FIFO mode, the spi controller shifts out the last 2 bytes that were written in a previous transfer on MOSI. This undocumented behaviour can cause devices to misinterpret the transfer, so we explicitly clear the WFIFO before each read. This behaviour was noticed on EspressoBin. Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-12spi: orion: Fix clock resource by adding an optional bus clockGregory CLEMENT1-0/+14
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock is optional because not all the SoCs need them but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly as well as mentioning the mandatory clock which was also missing. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-08spi: s3c64xx: add SPDX identifierAndi Shyti1-14/+4
Replace the original license statement with the SPDX identifier. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-08spi: imx: do not access registers while clocks disabledStefan Agner1-2/+13
Since clocks are disabled except during message transfer clocks are also disabled when spi_imx_remove gets called. Accessing registers leads to a freeeze at least on a i.MX 6ULL. Enable clocks before disabling accessing the MXC_CSPICTRL register. Fixes: 9e556dcc55774 ("spi: spi-imx: only enable the clocks when we start to transfer a message") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2018-01-05spi: atmel: Implements transfers with bounce bufferRadu Pirea1-29/+84
This patch enables SPI DMA transfers for Atmel SAM9 SoCs and implements a bounce buffer for transfers which have vmalloc allocated buffers. Those buffers are not cache coherent even if they have been transformed into sg lists. UBIFS is affected by this cache coherency issue. In this patch I also reverted "spi: atmel: fix corrupted data issue on SAM9 family SoCs"(7094576ccdc3acfe1e06a1e2ab547add375baf7f). Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-03spi: sh-msiof: Fix timeout failures for TX-only DMA transfersGeert Uytterhoeven1-1/+11
When using RX (with or without TX), the DMA interrupt triggers completion when the RX FIFO has been emptied, i.e. after the full transfer has finished. However, when using TX without RX, the DMA interrupt triggers completion as soon as the DMA engine has filled the TX FIFO, i.e. before the full transfer has finished. Then sh_msiof_modify_ctr_wait() will spin until the transfer has really finished and the TFSE bit is cleared, for at most 1 ms. For slow speeds and/or large transfers, this may cause timeouts and transfer failures: spi_sh_msiof e6e10000.spi: failed to shut down hardware 74x164 spi2.0: SPI transfer failed: -110 spi_master spi2: failed to transfer one message from queue 74x164 spi2.0: Failed writing: -110 Fix this by waiting explicitly until the TX FIFO has been emptied. Based on a patch in the BSP by Hiromitsu Yamasaki. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-03spi: spi-fsl-dspi: account for const type of of_device_id.dataJulia Lawall1-4/+3
This driver creates a number of const structures that it stores in the data field of an of_device_id array. The data field of an of_device_id structure has type const void *, so there is no need for a const-discarding cast when putting const values into such a structure. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-03spi: bcm53xx: simplify reading SPI dataRafał Miłecki1-16/+10
This commit makes transfer function use spi_transfer_is_last to determine if currently processed transfer is the last one. Thanks to that we finally set hardware registers properly and it makes controller behave the way it's expected to. This allows simplifying read function which can now simply start reading from the slot 0 instead of the last saved offset. It has been successfully tested using spi_write_then_read. Moreover this change fixes handling messages with two writing transfers. It's important for SPI flash devices as their drivers commonly use one transfer for a command and another one for data. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-03spi: sirf: account for const type of of_device_id.dataJulia Lawall1-2/+2
This driver creates various const structures that it stores in the data field of an of_device_id array. Adding const to the declaration of the location that receives the const value from the data field ensures that the compiler will continue to check that the value is not modified. Furthermore, the const-discarding cast on the extraction from the data field is no longer needed. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-22spi: pxa2xx: Use gpiod_put() not gpiod_free()Mark Brown1-2/+2
gpiod_free() is an internal function for gpiolib, gpiod_put() is the correct external function. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Suggested-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-21spi: pxa2xx: avoid redundant gpio_to_desc(desc_to_gpio()) round-tripRasmus Villemoes1-2/+2
gpio_free(gpio) simply does gpiod_free(gpio_to_desc(gpio)), so it's simpler and cleaner to use gpiod_free directly. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-19Merge remote-tracking branches 'spi/fix/armada', 'spi/fix/atmel', ↵Mark Brown5-4/+23
'spi/fix/doc', 'spi/fix/imx', 'spi/fix/rspi', 'spi/fix/sun4i' and 'spi/fix/xilinx' into spi-linus
2017-12-19spi: atmel: fixed spin_lock usage inside atmel_spi_removeRadu Pirea1-1/+1
The only part of atmel_spi_remove which needs to be atomic is hardware reset. atmel_spi_stop_dma calls dma_terminate_all and this needs interrupts enabled. atmel_spi_release_dma calls dma_release_channel and dma_release_channel locks a mutex inside of spin_lock. So the call of these functions can't be inside a spin_lock. Reported-by: Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Implement cs-gpios configurationGeert Uytterhoeven1-7/+59
The current support for GPIO chip selects assumes the GPIOs have been configured by platform code or the boot loader. This includes pinmux setup and GPIO direction. Hence it does not work as expected when just described in DT using the "cs-gpios" property. Fix this by: 1. using devm_gpiod_get_index() to request the GPIO, and thus configure pinmux, if needed, 2. configuring the GPIO direction is the spi_master.setup() callback. Use gpio_is_valid() instead of a check on positive numbers. Note that when using GPIO chip selects, at least one native chip select must be left unused, as that native chip select will be driven anyway, and (global) native chip select polarity must be taken into account. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Extend support to 3 native chip selectsGeert Uytterhoeven1-5/+13
Currently only the MSIOF_SYNC signal can be used as a native chip select. Extend support to up to 3 native chipselects using the MSIOF_SS1 and MSIOF_SS2 signals. Inspired by a patch in the BSP by Hiromitsu Yamasaki. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Avoid writing to registers from spi_master.setup()Geert Uytterhoeven1-11/+24
The spi_master.setup() callback must not change configuration registers, as that could corrupt I/O that is in progress for other SPI slaves. The only exception is the configuration of the native chip select polarity in SPI master mode, as a wrong chip select polarity will cause havoc during all future transfers to any other SPI slave. Hence stop writing to registers in sh_msiof_spi_setup(), unless it is the first call for a controller using a native chip select, or unless native chip select polarity has changed (note that you'll loose anyway if I/O is in progress). Even then, only do what is strictly necessary, instead of calling sh_msiof_spi_set_pin_regs(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-13spi: jcore: disable clock when registering spi conroller failedTakuo Koguchi1-1/+3
When probe function fails in registering the spi controller, the clock should remain disabled. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Takuo Koguchi <takuo.koguchi.sw@hitachi.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-12spi: davinci: Initialize dspi->done before any possible use of itMichele Dionisio1-2/+2
On SOC with multiple cpu (like omal l138) it is possible that spi periferic is already initialized when this module is loaded and so it is possible to recieve interrupt when the modules is not fully initialized. this patch initialize dspi->done before refister the interrupt handler that use it Signed-off-by: Michele Dionisio <michele.dionisio@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-07spi: sun6i: disable/unprepare clocks on removeTobias Jordan1-1/+1
sun6i_spi_probe() uses sun6i_spi_runtime_resume() to prepare/enable clocks, so sun6i_spi_remove() should use sun6i_spi_runtime_suspend() to disable/unprepare them if we're not suspended. Replacing pm_runtime_disable() by pm_runtime_force_suspend() will ensure that sun6i_spi_runtime_suspend() is called if needed. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 3558fe900e8af (spi: sunxi: Add Allwinner A31 SPI controller driver) Signed-off-by: Tobias Jordan <Tobias.Jordan@elektrobit.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-07spi: sun4i: disable clocks in the remove functionTakuo Koguchi1-1/+1
mclk and hclk need to be disabled. Since pm_runtime_disable does not disable the clocks, use pm_runtime_force_suspend instead. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Takuo Koguchi <takuo.koguchi.sw@hitachi.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-07spi: rspi: Do not set SPCR_SPE in qspi_set_config_register()Geert Uytterhoeven1-2/+2
The R-Car Gen2 Hardware User Manual Rev. 2.00 states: If the master/slave mode select bit (MSTR) is modified while the SPI function enable bit (SPE) is set to 1 (that is, this module is enabled), the subsequent operation cannot be guaranteed. Hence do not set SPCR_SPE when setting SPCR_MSTR, just like the .set_config_register() implementations for other RSPI variants do. Note that when booted from QSPI, the boot loader will have set SPCR_MSTR already, hence usually the bit is never modified by the Linux driver. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-30spi: sh-msiof: Use dev_warn_once() instead of open-codingGeert Uytterhoeven1-3/+2
Use the helper introduced by commit e135303bd5bebcd2 ("device: Add dev_<level>_once variants") instead of open-coding the same functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-28spi: meson-axg: add SPICC driver supportSunny Luo1-0/+1
Add new compatible string to support SPICC controller which found at Amlogic Meson-AXG SoC. This is aiming at adding a couple of enhanced feature patches. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-27spi: xilinx: Add support for xlnx,axi-quad-spi-1.00.aRicardo Ribalda1-0/+1
The driver has been successfully tested with Xilinx's core axi-quad-spi-1.0.0a. Documented on DS843: https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v1_00_a/ds843_axi_quad_spi.pdf Cc: Mark Brown <broonie@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-27spi: a3700: Fix clk prescaling for coefficient over 15Maxime Chevallier1-0/+8
The Armada 3700 SPI controller has 2 ranges of prescaler coefficients. One ranging from 0 to 15 by steps of 1, and one ranging from 0 to 30 by steps of 2. This commit fixes the prescaler coefficients that are over 15 so that it uses the correct range of values. The prescaling coefficient is rounded to the upper value if it is odd. This was tested on Espressobin with spidev and a locigal analyser. Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2017-11-24spi: xilinx: Detect stall with Unknown commandsRicardo Ribalda1-0/+11
When the core is configured in C_SPI_MODE > 0, it integrates a lookup table that automatically configures the core in dual or quad mode based on the command (first byte on the tx fifo). Unfortunately, that list mode_?_memoy_*.mif does not contain all the supported commands by the flash. Since 4.14 spi-nor automatically tries to probe the flash using SFDP (command 0x5a), and that command is not part of the list_mode table. Whit the right combination of C_SPI_MODE and C_SPI_MEMORY this leads into a stall that can only be recovered with a soft rest. This patch detects this kind of stall and returns -EIO to the caller on those commands. spi-nor can handle this error properly: m25p80 spi0.0: Detected stall. Check C_SPI_MODE and C_SPI_MEMORY. 0x21 0x2404 m25p80 spi0.0: SPI transfer failed: -5 spi_master spi0: failed to transfer one message from queue m25p80 spi0.0: s25sl064p (8192 Kbytes) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2017-11-16spi: spi-fsl-dspi: add SPI_LSB_FIRST to driver capabilitiesKurt Kanzenbach1-1/+1
The driver as well as the controller support the SPI lsb first mode. However, it's not possible to configure it e.g. when using spidev. Adding this flag to mode_bits resolves the issue and lsb first mode can be used. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-10Merge remote-tracking branches 'spi/topic/sh-msiof', 'spi/topic/slave', ↵Mark Brown5-13/+433
'spi/topic/spreadtrum' and 'spi/topic/tegra114' into spi-next
2017-11-10Merge remote-tracking branches 'spi/topic/imx', 'spi/topic/mxs', ↵Mark Brown5-60/+326
'spi/topic/orion', 'spi/topic/rspi' and 'spi/topic/s3c64xx' into spi-next
2017-11-10Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/axi', ↵Mark Brown4-36/+53
'spi/topic/davinci' and 'spi/topic/fsl-dspi' into spi-next
2017-11-10Merge remote-tracking branch 'spi/topic/core' into spi-nextMark Brown1-1/+3
2017-11-10Merge remote-tracking branches 'spi/fix/idr' and 'spi/fix/sh-msiof' into ↵Mark Brown2-3/+4
spi-linus
2017-11-10spi: imx: Don't require platform data chipselect arrayTrent Piepho1-7/+9
If the array is not present, assume all chip selects are native. This is the standard behavior for SPI masters configured via the device tree and the behavior of this driver as well when it is configured via device tree. This reduces platform data vs DT differences and allows most of the platform data based boards to remove their chip select arrays. CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <kernel@pengutronix.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Mark Brown <broonie@kernel.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-10spi: imx: Fix failure path leak on GPIO request errorTrent Piepho1-1/+3
If the code that requests any chip select GPIOs fails, the cleanup of spi_bitbang_start() by calling spi_bitbang_stop() is not done. Add this to the failure path. Note that spi_bitbang_start() has to be called before requesting GPIOs because the GPIO data in the spi master is populated when the master is registed, and that doesn't happen until spi_bitbang_start() is called. CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <kernel@pengutronix.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Mark Brown <broonie@kernel.org> CC: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-10spi: imx: GPIO based chip selects should not be requiredTrent Piepho1-8/+10
The driver will fail to load if no gpio chip selects are specified, this patch changes this so that it no longer fails. It's possible to use all native chip selects, in which case there is no reason to have a gpio chip select array. This is what happens if the *optional* device tree property "cs-gpios" is omitted. The spi core already checks for the absence of gpio chip selects in the master and assigns any slaves the gpio_cs value of -ENOENT. Also have the driver respect the standard SPI device tree property "num-cs" to allow setting the number of chip selects without using cs-gpios. CC: Mark Brown <broonie@kernel.org> CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <kernel@pengutronix.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07spi: imx: Fix failure path leak on GPIO request error correctlyTrent Piepho1-7/+8
In commit 974488e4ce1e ("spi: imx: Fix failure path leak on GPIO request error"), spi_bitbang_start() was moved later in the probe sequence. But this doesn't work, as spi_bitbang_start() has to be called before requesting GPIOs because the GPIO data in the spi master is populated when the master is registed, and that doesn't happen until spi_bitbang_start() is called. The default only works if one uses one CS. So add a failure path call to spi_bitbang_stop() to fix the leak. CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <kernel@pengutronix.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Mark Brown <broonie@kernel.org> CC: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-03spi: sh-msiof: remove redundant pointer devColin Ian King1-2/+0
The pointer dev is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/spi/spi-sh-msiof.c:1198:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-03spi: s3c64xx: remove redundant pointer sciColin Ian King1-3/+0
The pointer sci is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/spi/spi-s3c64xx.c:791:2: warning: Value stored to 'sci' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>

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