tag namedrm-intel-next-2017-12-22 (515bbc6063b5b9ee41dc77dabcfee43b56f72553)
tag date2017-12-22 11:42:32 -0800
tagged byRodrigo Vivi <rodrigo.vivi@intel.com>
tagged objectcommit cfe4982ca4...
- Allow internal page allocation to fail (Chris)
- More improvements on logs, dumps, and trace (Chris, Michal) - Coffee Lake important fix for stolen memory (Lucas) - Continue to make GPU reset more robust as well improving selftest coverage for it (Chris) - Unifying debugfs return codes (Michal) - Using existing helper for testing obj pages (Matthew) - Organize and improve gem_request tracepoints (Lionel) - Protect DDI port to DPLL map from theoretical race (Rodrigo) - ... and consequently fixing the indentation on this DDI clk selection function (Chris) - ... and consequently properly serializing non-blocking modesets (Ville) - Add support for horizontal plane flipping on Cannonlake (Joonas) - Two Cannonlake Workarounds for better stability (Rafael) - Fix mess around PSR registers (DK) - More Coffee Lake PCI IDs (Rodrigo) - Remove CSS modifiers on pipe C of Geminilake (Krisman) - Disable all planes for load detection (Ville) - Reorg on i915 display headers (Michal) - Avoid enabling movntdqa optimization on hypervisor guest (Changbin) GVT: - more mmio switch optimization (Weinan) - cleanup i915_reg_t vs. offset usage (Zhenyu) - move write protect handler out of mmio handler (Zhenyu) -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJaPXCRAAoJEPpiX2QO6xPKxi4IAJmAQCVBEZVz2TI/t6xJIYcl xGXlghAVlF8i2bRPpi8PioqUbASF1o7sIVjwIWEV+DgrIQT4MQCv1BmqvExlftBw 5mgkKyS+7Itnp7vaioYRmF/YxMoqP1vHF4J6fBScmtHf+RKtlwXQzw+AnlJtg88h d9mudeDzV5UXB2Prntia3w3sb6oJVKbtgeo+njll2SL6EPaz0sKBEuhcJkKWygtH 4gfneJG0cwIA/rJe4+eIfpnHRiXhhiwofPBYV0eWhBTTo47sKyGxfjpxmEEax1DF 3JUUe9a+2dYqXxOyhLlZEOeCfkcXhkgDmvJTlupWGVV3POIncNlt60lhmuS4t5g= =wJGr -----END PGP SIGNATURE-----

Privacy Policy