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authorAtish Patra <atishp@rivosinc.com>2022-07-11 10:46:31 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2022-08-11 14:58:22 -0700
commit63ba67ebdfd403ef53aa0fefde3a42e505516e8c (patch)
tree48b5c635053d3988ee379dfa762fcce7571ef99f /drivers
parent0209b5830bea42dd3ce33ab0397231e67ec3b751 (diff)
RISC-V: Move counter info definition to sbi header file
Counter info encoding format is defined by the SBI specificaiton. KVM implementation of SBI PMU extension will also leverage this definition. Move the definition to common sbi header file from the sbi pmu driver. Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20220711174632.4186047-5-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/perf/riscv_pmu_sbi.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index bae614c73b14..24124546844c 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -21,20 +21,6 @@
#include <asm/sbi.h>
#include <asm/hwcap.h>
-union sbi_pmu_ctr_info {
- unsigned long value;
- struct {
- unsigned long csr:12;
- unsigned long width:6;
-#if __riscv_xlen == 32
- unsigned long reserved:13;
-#else
- unsigned long reserved:45;
-#endif
- unsigned long type:1;
- };
-};
-
/*
* RISC-V doesn't have hetergenous harts yet. This need to be part of
* per_cpu in case of harts with different pmu counters

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