AgeCommit message (Expand)AuthorFilesLines
2020-12-10media: docs: uAPI: fix table output in LaTeX/PDF formatmedia/v5.10-5Mauro Carvalho Chehab90-301/+669
2020-12-10media: pixfmt-yuv-planar.rst: fix PDF OUTPUTMauro Carvalho Chehab1-9/+25
2020-12-10media: ext-ctrls-codec-stateless.rst: fix an H-264 table formatMauro Carvalho Chehab1-11/+25
2020-12-10media: buffer.rst: fix a PDF output issueMauro Carvalho Chehab1-4/+4
2020-12-10media: docs: pixfmt: use section titles for bayer formatsMauro Carvalho Chehab4-1/+8
2020-12-10media: ext-ctrls-jpeg.rst: cleanup V4L2_CID_JPEG_COMPRESSION_QUALITY textMauro Carvalho Chehab1-7/+6
2020-12-10media: ext-ctrls-codec.rst: simplify a few tablesMauro Carvalho Chehab1-59/+19
2020-12-10media: ext-ctrls-codec.rst: add a missing profile descriptionMauro Carvalho Chehab1-1/+1
2020-12-10media: ext-ctrls-codec-stateless.rst: change a FWHT flag descriptionMauro Carvalho Chehab1-1/+1
2020-12-10media: docs: sliced-vbi: fix V4L2_SLICED_WSS_625 docsMauro Carvalho Chehab2-14/+33
2020-12-10media: control.rst: use a table for V4L2_CID_POWER_LINEMauro Carvalho Chehab1-4/+7
2020-12-10media: colorspaces-details.rst: drop tabularcolumnsMauro Carvalho Chehab1-31/+0
2020-12-10docs: conf.py: fix sphinx version detection for margin setMauro Carvalho Chehab1-1/+2
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwaremedia/v5.11-1Sakari Ailus1-0/+4
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus1-0/+5
2020-12-07media: ccs: Print written register valuesSakari Ailus1-0/+4
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus1-1/+8
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus2-20/+46
2020-12-07media: ccs: Dual PLL supportSakari Ailus2-3/+51
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus2-22/+196
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus1-27/+37
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus1-5/+7
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus1-26/+25
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus2-57/+95
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus1-19/+66
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus1-23/+31
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus3-29/+64
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus1-124/+131
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus1-9/+26
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus1-0/+9
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus3-8/+23
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus3-6/+16
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus3-1/+7
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus4-19/+23
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus1-1/+10
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus2-11/+31
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus1-2/+2
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus1-2/+1
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus1-2/+9
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus1-8/+4
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus1-2/+5
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus1-0/+89
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus3-3/+4
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus2-15/+4
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus1-2/+8
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus1-2/+2
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus3-188/+209

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