aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h
blob: c801ddd7119247ccc55f9923a6bc541343a26f4d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Support for Intel Camera Imaging ISP subsystem.
 * Copyright (c) 2015, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _input_system_ctrl_defs_h
#define _input_system_ctrl_defs_h

#define _INPUT_SYSTEM_CTRL_REG_ALIGN                    4  /* assuming 32 bit control bus width */

/* --------------------------------------------------*/

/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/

// Number of registers
#define ISYS_CTRL_NOF_REGS                              23

// Register id's of MMIO slave accesible registers
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID              0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID              1
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID              2
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID         3
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID         4
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID         5
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID         6
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID         7
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID         8
#define ISYS_CTRL_ACQ_START_ADDR_REG_ID                 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID            10
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID            11
#define ISYS_CTRL_INIT_REG_ID                           12
#define ISYS_CTRL_LAST_COMMAND_REG_ID                   13
#define ISYS_CTRL_NEXT_COMMAND_REG_ID                   14
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID               15
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID               16
#define ISYS_CTRL_FSM_STATE_INFO_REG_ID                 17
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID          18
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID          19
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID          20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID             21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID    22

/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL      3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL      3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL      3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL              0
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL         128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL         3
#define ISYS_CTRL_INIT_REG_RSTVAL                        0
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL              0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL          0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0

/* register width value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH            9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH            9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH            9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH       9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH       9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH       9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH               9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH          9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH          9
#define ISYS_CTRL_INIT_REG_WIDTH                         3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH                 32    /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH                 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH             32
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH             32
#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH               32
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH           32
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH  1

/* bit definitions */

/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/

/*
InpSysCaptFramesAcq  1/0  [3:0] - 'b0000
[7:4] - CaptPortId,
	   CaptA-'b0000
	   CaptB-'b0001
	   CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt  2/0  [3:0] - 'b0001'
[7:4] - CaptPortId,
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC

  2/1  [31:0] - external capture address
InpSysAcqFrame  2/0  [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
  2/1  [31:0] - external memory read start address
InpSysOverruleON  1/0  [3:0] - 'b0011,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

InpSysOverruleOFF  1/0  [3:0] - 'b0100,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

InpSysOverruleCmd  2/0  [3:0] - 'b0101,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

  2/1  [31:0] - command token value for port opid

acknowledge tokens:

InpSysAckCFA  1/0   [3:0] - 'b0000
 [7:4] - CaptPortId,
	   CaptA-'b0000
	   CaptB- 'b0001
	   CaptC-'b0010
 [31:16] - NOF_frames
InpSysAckCFE  1/0  [3:0] - 'b0001'
[7:4] - CaptPortId,
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC

InpSysAckAF  1/0  [3:0] - 'b0010
InpSysAckOverruleON  1/0  [3:0] - 'b0011,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

InpSysAckOverruleOFF  1/0  [3:0] - 'b0100,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

InpSysAckOverrule  2/0  [3:0] - 'b0101,
[7:4] - overrule port id (opid)
	   'b0000 - CaptA
	   'b0001 - CaptB
	   'b0010 - CaptC
	   'b0011 - Acq
	   'b0100 - DMA

  2/1  [31:0] - acknowledge token value from port opid

*/

/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID        0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID         1 /* 0001b */
#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID              2 /* 0010b */
#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID            3 /* 0011b */
#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID           4 /* 0100b */
#define ISYS_CTRL_OVERRULE_TOKEN_ID               5 /* 0101b */

#define ISYS_CTRL_ACK_CFA_TOKEN_ID                0
#define ISYS_CTRL_ACK_CFE_TOKEN_ID                1
#define ISYS_CTRL_ACK_AF_TOKEN_ID                 2
#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID        3
#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID       4
#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID           5
#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID       6

#define ISYS_CTRL_TOKEN_ID_MSB                    3
#define ISYS_CTRL_TOKEN_ID_LSB                    0
#define ISYS_CTRL_PORT_ID_TOKEN_MSB               7
#define ISYS_CTRL_PORT_ID_TOKEN_LSB               4
#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB              31
#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB              16
#define ISYS_CTRL_NOF_EXT_TOKEN_MSB               31
#define ISYS_CTRL_NOF_EXT_TOKEN_LSB               8

#define ISYS_CTRL_TOKEN_ID_IDX                    0
#define ISYS_CTRL_TOKEN_ID_BITS                   (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX                     (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
#define ISYS_CTRL_PORT_ID_BITS                    (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_CAPT_IDX                    ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS                   (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_EXT_IDX                     ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS                    (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)

#define ISYS_CTRL_PORT_ID_CAPT_A                  0 /* device ID for capture unit A      */
#define ISYS_CTRL_PORT_ID_CAPT_B                  1 /* device ID for capture unit B      */
#define ISYS_CTRL_PORT_ID_CAPT_C                  2 /* device ID for capture unit C      */
#define ISYS_CTRL_PORT_ID_ACQUISITION             3 /* device ID for acquistion unit     */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_A              4 /* device ID for dma unit            */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_B              5 /* device ID for dma unit            */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_C              6 /* device ID for dma unit            */
#define ISYS_CTRL_PORT_ID_DMA_ACQ                 7 /* device ID for dma unit            */

#define ISYS_CTRL_NO_ACQ_ACK                      16 /* no ack from acquisition unit */
#define ISYS_CTRL_NO_DMA_ACK                      0
#define ISYS_CTRL_NO_CAPT_ACK                     16

#endif /* _input_system_ctrl_defs_h */

Privacy Policy